Z80 and R800 Assembly/Machine Language Op-code Tables

Written by "Cyberknight" Masao Kawata.
E-Mail: cyber_unicorn@hotmail.com
Revised: 1997-November-19 Wednesday.

These tables are compilations of different sources, including Z80 instruction set tables and an article of the Japanese "MSX Magazine" (issue of 1990-Nov.) with R800 Assembly.

Tables entries:

Z80 Assembly: Z80 official Assembly instructions.
R800 Assembly: R800 official Assembly instructions.
Operation: description of instruction's operations in symbolic language.
Description: description of instruction in natural language.
Remarks: remarks about the instruction.

Flags: description of register F bits' reaction to the instruction execution:

.	(flag not modified)
*	(flag modified by the instruction)
0	(flag reset), 1 (flag set)
p	("parity/overflow" flag indicates parity)
o	("parity/overflow" flag indicates overflow state)
?	(flag result is unknown)
$	(if .bc becomes zero, flag is set to 0, else to 1)
%	(if .a = [.hl], then flag is set to 1, else to 0)
!	(if .b becomes zero, flag is set to 1, else to 0)
I	(copies the value of IFF into the flag)

The flags are:

S	(sign, .f{7})
Z	(zero, .f{6})
H	(half-carry, .f{4})
P	(parity/overflow, .f{3})
N	(subtraction, .f{1})
C	(carry, .f{0})

Op-codes: the codes in Machine Language (binary and hexadecimal [Hex]).
B: length of the instruction in bytes.
Z*: time spent by a Z80 to execute the instruction, in clock cycles.
R*: time spent by a R800 to execute the instruction, in clock cycles.

* The time spent by each instruction depends on the hardware architecture. MSX uses RAS/CAS memory banks, so some "wait states" may be generated when accessing memory, even when just reading the program op-codes. MSX turbo R is somehow optimized so it avoids some wait-states when running in R800 mode.

Definitions used in the tables:

Z80 8 bit registers

000 001 010 011 100 101 110 111

r b c d e h l a

u b c d e a

v b c d e a

R800 8 bit registers

000 001 010 011 100 101 110 111

r .b .c .d .e .h l .a

u .b .c .d .e .ixh .ixl .a

v .b .c .d .e .iyh .iyl .a

p .ixh .ixl

q .iyh .iyl

Z80 16 bit registers

00 01 10 11

rr bc de hl af

ss bc de hl sp

pp bc de ix sp

qq bc de iy sp

R800 16 bit registers

00 01 10 11

rr .bc .de .hl .af

ss .bc .de .hl .sp

pp .bc .de .ix .sp

qq .bc .de .iy .sp

Other Registers

Z80 R800 Name

i .i interrupt vector

r .r refresh register

pc .pc program counter

Bits

{b} bit b (3 bits number)

{x..y} bit range x..y

IFF interrupt flip-flop

C 1st bit of .f

N 2nd bit of .f

P 4th bit of .f

H 5th bit of .f

Z 7th bit of .f

S 8th bit of .f

Index Register Modifiers (Z80/R800)

Bin
Hex DDH
11011101 FDH
11111101

ii ix/.ix iy/.iy

Reset/Break Addresses

000 001 010 011 100 101 110 111

k 00H 08H 10H 18H 20H 28H 30H 38H

Symbolic operands

+ add

- subtract

× multiply

÷ divide

<< assign

<=> exchange

< less than

> greater than

= equal

[n] I/O port n

[.c] I/O port defined by .c

[nn] address pointer

Numbers

n 8 bits

d -128..+127

nn 16 bits

nnl nn "LSB"

nnh nn "MSB"

Logical Operations

¬ not

& and

# or

^ xor

Symbolic registers

ssl ss LSB

ssh ss MSB

rrl rr LSB

rrh rr MSB

iil ii LSB

iih ii MSB

pcl pc/.pc LSB

pch pc/.pc MSB

tmp temporary

Notes:

Some R800 exclusive instructions may also work on most Z80, but it's not granted. To support compatibility, don't use them in MSX programs. Multiplication instruction are known to work only with R800.
The destiny address off-set of all relative jumps is calculated based on the next address immediately after the jump op-code itself. Thus, a zero off-set will make the processor jump exactly to the next instruction (it will execute the next instruction as if no jump was made); a -2 off-set will make the processor jump back to the jump op-code itself, because all relative jump op-codes are 2 bytes long, and so on. It is valid also to the DJNZ/DBNZ instruction.
The EX AF,AF'/XCH .AF,.AF' and POP AF/POP .AF instructions does not modify any flag by themselves, but, due to their operations, value of register F may be changed.
Assembly instructions that use index registers IX or IY and requires a numeric off-set may have it ommited if off-set is zero. Examples: "ld a,(ix+0)" may appear as "ld a,(ix)"; "bit 0,[.ix+0]" may appear as "bit 0,[.ix]". Of course, the machine op-codes are not affected, ever presenting the off-set, even if it is zero.
SHL and SHLA instructions of the R800 are the same, but with two different mnemonics defined, so they can "pair" the SHR and SHRA instruction mnemonics.
Some op-codes are equivalent, performing the same operations, so they are assigned to the same mnemonics.
There are currently three tables available: compact, sorted by instruction and sorted by op-code.

Z80 8 bit registers
	000	001	010	011	100	101	110	111
r	b	c	d	e	h	l		a
u	b	c	d	e				a
v	b	c	d	e				a

R800 8 bit registers
	000	001	010	011	100	101	110	111
r	.b	.c	.d	.e	.h	l		.a
u	.b	.c	.d	.e	.ixh	.ixl		.a
v	.b	.c	.d	.e	.iyh	.iyl		.a
p					.ixh	.ixl
q					.iyh	.iyl

Z80 16 bit registers
	00	01	10	11
rr	bc	de	hl	af
ss	bc	de	hl	sp
pp	bc	de	ix	sp
qq	bc	de	iy	sp

R800 16 bit registers
	00	01	10	11
rr	.bc	.de	.hl	.af
ss	.bc	.de	.hl	.sp
pp	.bc	.de	.ix	.sp
qq	.bc	.de	.iy	.sp

Other Registers
Z80	R800	Name
i	.i	interrupt vector
r	.r	refresh register
pc	.pc	program counter

Bits
{b}	bit b (3 bits number)
{x..y}	bit range x..y
IFF	interrupt flip-flop
C	1st bit of .f
N	2nd bit of .f
P	4th bit of .f
H	5th bit of .f
Z	7th bit of .f
S	8th bit of .f

Index Register Modifiers (Z80/R800)
Bin Hex	DDH 11011101	FDH 11111101
ii	ix/.ix	iy/.iy

Reset/Break Addresses
	000	001	010	011	100	101	110	111
k	00H	08H	10H	18H	20H	28H	30H	38H

Symbolic operands
+	add
-	subtract
×	multiply
÷	divide
<<	assign
<=>	exchange
<	less than
>	greater than
=	equal
[n]	I/O port n
[.c]	I/O port defined by .c
[nn]	address pointer

Symbolic registers
ssl	ss LSB
ssh	ss MSB
rrl	rr LSB
rrh	rr MSB
iil	ii LSB
iih	ii MSB
pcl	pc/.pc LSB
pch	pc/.pc MSB
tmp	temporary