BIOS Release Notes Version 4.18.20.34.13 BIOS VGA Support As shown in Table 1.1 and Table 1.2, the latest NVIDIA BIOS releases support the IBM VGA standard 7-bit modes and VESA modes. IBM VGA Modes The supported IBM VGA modes are shown in Table 1.1. Table 1.1 Supported IBM VGA Modes Mode Colors Resolution Memory 00/01 16 40x25 Text (As 0+/1+ 400 line modes) 02/03 16 80x25 Text (As 2+/3+ 400 line modes) 04/05 4 320x200 2-bit Planar 06 2 640x200 1-bit Planar 07 Mono 80x25 Text 08-0C Reserved Reserved Reserved 0D 16 320x200 4-bit Planar 0E 16 640x200 4-bit Planar 0F Mono 640x350 1-bit Planar (Uses white text) 10 16 640x350 4-bit Planar 11 2 640x480 2-bit Planar 12 16 640x480 4-bit Planar 13 256 320x200 8-bit Packed VESA Modes Table 1.2 shows supported VESA modes. Table 1.2 Supported VESA Modes VESA Colors Resolution Memory 100h 256 640x400 8-bit Packed 101h 256 640x480 8-bit Packed 102h 16 800x600 4-bit Planar 103h 256 800x600 8-bit Packed 104h 16 1024x768 4-bit Planar 105h 256 1024x768 8-bit Packed 106h 16 1280x1024 4-bit Planar 107h 256 1280x1024 8-bit Packed 10Eh 64 K 320x200 16-bit Packed 10Fh 1.6 M 320x200 32-bit Packed 111h 64 K 640x480 16-bit Packed 112h 1.6 M 640x480 32-bit Packed 114h 64 K 800x600 16-bit Packed 115h 1.6 M 800x600 32-bit Packed 117h 64 K 1024x768 16-bit Packed 118h 1.6 M 1024x768 32-bit Packed 11Ah 64 K 1280x1024 16-bit Packed 130h 256 320x200 8-bit Packed 131h 256 320x400 8-bit Packed 132h 64 K 320x400 16-bit Packed 133h 1.6 M 320x400 32-bit Packed 134h 256 320x240 8-bit Packed 135h 64 K 320x240 16-bit Packed 136h 1.6 M 320x240 32-bit Packed 13Dh 64 K 640x400 16-bit Packed 13Eh 1.6 M 640x400 32-bit Packed 145h 256 1600x1200 8-bit Packed 146h 64 K 1600x1200 16-bit Packed Known NV18 BIOS Limitations This section describes problems that either cannot or will not be fixed by NVIDIA. Usually, the source of the problem is beyond the control of NVIDIA. The list of problems follows: • “AMIDiag 6.0 VESA Video Memory Test Failure” • “Vesatest Reports Mode 03H Does Not Work” AMIDiag 6.0 VESA Video Memory Test Failure Running the VESA Video Memory Test in AMI Diagnostic 6.0 generates the following error message: “VESA video memory test failed.” This occurs because AMI Diagnostic is using the total video memory to calculate the number of 64 KB pages to test. Instead, the program should use GetVesaModeInfo() to find the number of available pages to test. The number of available pages is less than the calculated total because a portion of the video memory is write protected. Vesatest Reports Mode 03H Does Not Work Vesatest reports that the 0000h and 0002h modes of function 03H fail, regardless of the output device. This is caused by the Vesatest application looking for old IBM-compatible mode tables, which are not supported in the BIOS for Core 4 products, such as NV17. BIOS Release History This section describes problems that either cannot or will not be fixed by NVIDIA. Usually, the source of the problem is beyond the control of NVIDIA. The list of problems follows: 4.18.20.34.00 • Updated TMDS parameter for adjusted swing boards. • Changed to new TMDS PLL setting. • Added new small footprint build option for P111. • Added 16Mx16 support for P111 boards. • Because the driver turns off the syncs on 680848h, enabled the syncs here. DPMS disable could not fix it because of the save/restore added to this function. 4.18.20.33.00 • Added TMDSPLL reset on all chips with an internal TMDS. • Now, protect di when the dual-link bit is read so the pclk can still be read. • New PLL setting. 4.18.20.32.00 • Modified the VBE_SetDisplayStateEDCB2() routine to PUSH and POP ES. This fixed a bug where ES was being trashed during a display-switch call. • Updated the OEMSetRegs() routine to call AllocVStack() and FreeVStack() to create more stack space during a set mode call. This fixes the problem with Slovak/Slovenian Windows Me installation hanging during a set mode call due to running out of stack space during the OEMSetRegs() routine. • Before enabling the display during a mode set, the code first verifies whether the device has been disabled. If it has been disabled, then the display is not turned on. 4.18.20.28.00 • Changed PLL0 to 0x6d. • Moved a call to OEMInitExt() so it occurs after the KDA buffer initialization because the function uses the buffer. • Added a check inside WaitForVerticalRetrace() and WaitVerticalRetracePanel() to see if we are in POST. The check skips the actual wait for retrace if we are in POST to save time. • Instituted default builds of “functionality minimized” BIOSs (indicated by “fm” in the directory name), which are smaller than 48 KB during runtime. The images generated for fmnvXX and fmnvXXb are similar to those generated for smnvXX and smnvXXb and have the same set of scripts applied. The fm BIOS specifics are as follows: • Enabled discardable POST. • The only enabled VBE functions are 00, 01, 02, 03, 05, DPMS, and DDC. No OEM VBE functions are enabled. • Only TMDS tables are enabled; no TV or LVDS code or tables. • Added refresh rate limit support for flat panels. We set up a refresh rate range and only set the refresh rate if it falls into this range. We reject the ones that are out of range. • Took out the waiting in the panel-off script because we are polling AUX3 to make sure we don’t touch a TMDS-related register before the sequencer finishes its work. 4.18.20.27.00 • Implemented the PLL kick start sequence in devinit. • Interim DCB 3.0 check-in: • Modified defines in NVDEVICE for DCB 3.0 (DSI field defines, main DCB field). • Updated DCB header struct. • Updated DSI and base DCB structs. • Updated DCB.ASM functions to new defines so they compile. • Added DCB 3.0 build batch file. • Updated DCB reserved buffer calculation so it works correctly. • Added panel and mode support for 1440x900, 1680x1050, and 1920x1200. • Checked in DDR, DDR2, and DDR3 definitions. • In FPEXTLINK.ASM, updated the routine ProgramExternalTMDS to check for the External Encoder V_DCB22_DSI_LCD_EXTCHIP_SI164_ADR74 before defining the I2C device address to 0x74. 4.18.20.26.00 • Added new blind boot support. We only boot to blind bootable displays like CRTs, TVs, and strapping LCDs. Also, we use the BMP_DCBPOSTMaxNumOfHeads flag to determine how many blind boot devices we boot to. 4.18.20.25.00 • In order to speed up text scrolling, changed the definition for enable head A, head B, or broadcast mode. The old value was 00h/01h/80h/81h, the new value is 00h/03h/04h/07h. The new value matches the actual definition in CR44, saving unnecessary head A and head B access. 4.18.20.24.00 • Gave preference to setting 60-Hz modes instead of others when the mode has to be picked up from the established timings list. • The panel is now turned off before the panel timings are programmed. • This modification removed the following VESA modes to conserve space in the VBIOS: Mode 108: 80x60 text Mode 109: 132x25 text Mode 10A: 132x43 text Mode 10B: 132x50 text Mode 10C: 132x60 text 4.18.20.23.00 • Changed the TMDS limit to reflect the true chip capability and to get rid of the reduced blanking. • Added 800x600 panel support. • Added TMDS capability verification to the established modes programming branch. It forces the logic to skip a highest mode found from the list supported by the flat panel but not supported by the video card due to a maximum pclk chip limitation (in case of internal TMDS) or the board design specifics: internal or external TMDS and the capability of single or dual TMDS support. If it's found the board does not support the requested mode, the logic keeps parsing the established timings list until both the flat panel and video board are satisfied. • In the routine SignOn(), modified the vertical retrace delay to use the Delay() routine. 4.18.20.22.00 • Now, do spread spectrum on a per-panel strapping basis. In certain designs, a customer could have spread spectrum enabled on one panel and disabled on another panel. 4.18.20.21.00 There is new reduced blanking for TMDS 1006x1200 panel. 4.18.20.20.00 • Updated Hynix and Samsung E-die 8Mx16 NV_PFB_CFG. • Properly waiting for vsync fixed a brief horizontal flicker when a mode was set. It was necessary to take into account devices on a head—panel has priority over TV and CRT—but also to wait for a correct head. 4.18.20.19.00 • No longer touch cr28[5:3] when enabling DFP; those bits are meant for TV only. • Adjust CRTC vertical total when displaying to flat panel. It makes our vertical blanking look normal to Windows. 4.18.20.18.00 • Now, save the panel 0xF to our BOOT_0 register. • Changed Setmode() code for the last wait for retrace. The implementation was detecting only the internal panel to wait for sync in order to avoid setmode flicker on the panel (an OEM request). Changed the logic to default to a normal WaitForRetrace() in the case that panel is not on head B (which in itself is a special case). This fixes Setmode() corruption on CRT and TV when the device is not an internal panel. 4.18.20.17.00 • Increased TMDS capability to support 1600x1200 panels. • Added BMP pointers for Winbond part and I2C scripting table. • Updated external TMDS DFP programming to use I2C scripting. • Fixed a bug in the OemInitTV() routine, where an INT 15 callback, AX=5F01 TV-Type Override, caused a stack error. Moved the saving of the DCB index before the INT 15h call back. • Override crystal and TV type using ROM mask. • DPMS on, skip setting CR3B if a device is already on. It corrupted that register. • Implemented DDR memory initialization that conforms to the spec. • Added function GetATCState() to bypass the DPMS-on code if the DPMS is not active (displays are lit). This fixes a panel flash because we don’t have to reset the panel. • Updated VBE_ModeStatus() to check for accelerated mode on both heads and to return the combined value. • Set VBE mode info flags for modes 7A and higher to not support banking (LFB access only). 4.18.20.16.00 • Replaced the lea esi, [esi+eax+KDA_VSTACK_HEADER] instruction with set of two: add esi,eax add esi,KDA_VSTACK_HEADER that delivers an identical result. This helps to keep code functional on some IA64 systems whose x86 legacy emulator does not support this Pentium LEA instruction format. • Added new ESMT 8Mx16 memory support for P111. • Made sure link A/B LVDS script doesn’t shut down link C. This makes LVDS and TMDS work at the same time. • VBE_BankHandler() now returns non-failure for modes that require more than 4 MB. • Fixed UnBlankSR1() called by 4F14, 018A to preserve esi register so it is not trashed. • Reduced drive/slew table clock to 200 MHz for P162 per marketing spec change. • Bit [3] is now cleared in addition to bits [5] and [2] of CR28 when the flat panel (FP) is disabled. If this bit is left on when the next device to switch to is the TV, the TV will be corrupted. • Correctly set up the alternate selection in PLL 04 when link A is driven by head A in a single-link situation. • Bypass the Spread Spectrum enable in the case of desktop. The spread spectrum is used on mobile designs only and the GPIO driven for spread spectrum could be used for other purposes on desktop. • Updated 4F11h, VESA internal flat panel information request call to return the correct resolution for LVDS EDID panels. • Added CR1C[5] bit reset code to run each time the CR1B is programmed. The registers should be programmed together to provide proper burst value. Removed surplus call to GetCRTCAddr() from SetDefaultFIFO() for all modules. • NV_PRAMDAC_FP_DEBUG_2 register programming is now skipped for vertical total enable (the FPFixupScalingEDCB() routine) when the driver is active to assure the FP scaler is not switched out of the vertical total calculated from the CRTC register settings. • The panel sync polarity is now controlled by NV_PRAMDAC_FP_TG_CONTROL, leaving INDIR_TMDS_LVDS positive all the time. For the BIOS and driver, the sync & DE (data/display enable) polarities should only be controlled using NV_PRAMDAC_FP_TG_CONTROL. The polarity control in NV_PRAMDAC_INDIR_TMDS_LVDS should always be at the default, positive polarity. • In WaitVerticalRetraceHeadB() changed the time-out value to expire after 21 ms on a 2.2 GHz CPU (it was 1.1 GHz). In SetMode(), moved a call to OEMPostSetMode() to before the wait for retrace because this call takes longer in core4r2 than it did before. These changes fix corruption that occurred during mode sets on panels. • Set GPIO3 to output for NV18M. • Added initialization of NV_PRAMDAC_FP_TG_CONTROL @ 68x848[20:20]=1: _READ_PROG for both heads on all NV chips. This allows reads of HDISPLAY_END, VDISPLAY_END, HVALID_START, HVALID_END, VVALID_START, and VVALID_END to return the actual values programmed into the registers rather than the automatically calculated values, which may be modified by the settings of NV_PRAMDAC_FP_TG_CONTROL_MODE and NV_PRAMDAC_FP_TG_CONTROL_CENTER. This worked around an issue where reading and writing back the HVALID_START and HVALID_END registers while in centered mode “armed” the FP display so that a subsequent assertion of _MODE_SCALE showed a display that was clipped along the horizontal axis. • Fixed a bug in the bmp_NVClockInitTbl structure where it was not properly terminated with the INIT_DONE command. • Fixed a bug in the routine GetGPIO(). GPIO00 and GPIO01 were being ready from the wrong bit field. GPIO00 should be read from 680818[8] and GPIO01 should be read from 680818[24]. • LVDS is now capable of running off either head now; updated DCB. • Updated internal panel detection. For an EDID panel, detect panel presence based on the EDID. For a strapping panel, panel strapping ID 0xF or panel table ID 0xF indicate no panel. • Moved AutoDrvslwCopy() out of NV30.ASM into OEM.ASM. Moved the AutoDrvslwRiseTbl, AutoDrvslwFallTbl, and AutoDrvslwTermTbl into NV3xDATA.ASM. 4.18.20.15.00 • Added support for C116 DVI+CRT+TV flavor. • Fixed issue related to panels not being able to display FS-DOS modes. Added protection for the DS segment around the call to FP_DDC_InitEDCB() because it was being killed in that procedure, which caused the mode information to be read from the wrong segments. • Changed OEMEnableFPEDCB() to use an unsigned compare on EDID[79h], not a signed compare, when the FP type is NV_DCB20_REC_TYPE_LCD_LVDS. This is a more general trap for cases where EDID[79h] is neither 01=slink nor 02=dlink. 4.18.20.14.00 • Added code to skip vstack functionality in the main int10 handler for the function 4F05 to make it faster. • Moved the real mode access save and restore into SaveIndicesAndLock() and RestoreIndicesAndLock(). Because this is no longer done for every NV register access, the video BIOS is faster. Put PM function back to the normal location where it shares SaveIndices() and RestoreIndices(). Added a conversion for changing our chip PM off definition(03h) before calling VBE_SetPowerStateEDCB(). Moved csControllerEnableIO() and csControllerDisableIO() into util.asm because those functions should be common for every chip. • Added a real detect for EDID-based LCDs so CR3B correctly indicates if no LCD is attached. • Fixed a bug in the OEMEnableExtensions() and OEMDisableExtensions() where CR2C was being written to either head A or head B when it should have been written to head A only. CR2C on head B has a different definition, with which CR2C head B [0] skip-enables devices. • Added the script file and support for P111 SKU2. • Updated all NV18 scripts to use DCB 2.2. • Update SetupLinkHeadEDCB() to make sure it does not set up PLL04 twice for the dual link case. • Made sure LVDS panel is not turned off when TMDS panel is enabled. 4.18.20.13.00 • Preserved DCB entry si when calling FP_DDC_InitEDCB(), si is trashed when an EDID2.0 panel is connected and subsequently DVO doesn’t get enabled correctly. Fixes bug #64698. • Fixed EnableDVO() for chips with two DVOs so it correctly handles the DVO A only case. Also update DisableDVO() so it clears enable bits for a DVO on both heads. • Made OEMEnableTVEDCB() preserve all registers by also preserving BX. This fixes bug #65116. • Fixed PLL programming for FP to use ProgPLL() so it can handle both single and dual stage PLL programming correctly. This fixes bug #64795. • Change FPFixupScalingEDCB() to also assert NV_PRAMDAC_FP_DEBUG_0 @680880 [7:7]=1: _BLEND_LSBFILTER for all GPUs. Addresses bug #62134. • Added code to set and check vstack availability. 4.18.20.12.00 • Fixed code which tests FP_TABLE.Spread flags at POST using bad pointer. • Revisited 32-bit protected mode interface code to clean up of legacy NV11 code and chose better (shorter) instructions that save 316 bytes of code space. • Shut down link B TMDS properly. Fixes bug #58155. 4.18.20.11.00 • Added 24-bit panel support in NV17 and NV18. • Added the ability for all mobile systems to program their EDIDs. Deleted the build conditionals for NV_LVDS_EDID_WRITE. • Added BMP 5.22 support. • Skipped the 20 ms delay in IsMonitorDDC() if it is from flat-panel code. This enables video BIOS WHQL issue #58328 to pass. 4.18.20.10.00 • Script table re-organization. • Created nvxxscrtbl.scp table to save the init table so we don’t duplicate it in every script file. Just need ti include the new file instead. This also allows us to update the init table without breaking old script files. • Add bmp_FinalInitTbl. It is equal to the old bmp_ExtraInitTbl. We will not put anything in bmp_ExtraInitTbl in video BIOS source, freeing it up for OEMs to add things without breaking our script in bmp_FinalInitTbl. • Separated old clock table to nvclock and mclock table, making them independently changeable. • For mobile script table, re-wrote LVDS_ResetTbl update mechanism. Got rid of the old duplicated init tables. • Updated perl program to interpret the new table entries. • Added method to use Link information in an LVDS EDID at offset 79h. • Made NV_PBUS_FBIO_DLY part of the strapable register setting per application request: bug #56022. • Updated CR1C accesses in ReadROM() to use head A. This fixed problem of instance memory sometimes not getting unlocked (and the ROM copy failing). • Updated P111 memory timing for Hynix memory. • Change ProgCRTTimingSel() to UnProgTVTimingSel(). CR53 and CR54 for the LCD ALT timing selectors were being cleared in the TV-disable path. Fixed #61297. • Updated CalcMNP() to return correct frequency value (including values above 655.36 MHz). • Modified the BEEP() and BOOP() routines to use the WaitTicks() routine. • Commented out the routine WaitTimer(). 4.18.20.09.00 • Updated EnableDVO() to allow for a single DCB entry to enable both DVOs (DVO A and B are enabled separately on NV18). For P111, do not override AGP 8x enable/disable; let the board strapping do its work. • Updated the BMP structure to 2.1 with the addition of the MinMaxTempCntl data structure. The data structure contains thermal diode and fan temperature control data. • Added support for LCD external encoder types (DCB 2.2). Added support for dual-link mode with a single DVO port. On mode set, clear only the amount of memory that is required for a given mode. Fixed RFE #56609. • Updated linkC TMDS setting for frequencies below 108 MHz. • New linkC TMDS setting for frequencies between 108 MHz and 126 MHz. • Added support for dual-TMDS DFPs. This includes: • Supporting the DVO_A+DVO_B combo in a DCB entry. • Using IND1 (both heads) to store actual output device usage. • Updating all init scripts to clear IND1 during device init. • New setting for linkC TMDS PLL registers when frequency is >= 126 MHz. Fixed bug #61639. • In MEMCFG.ASM, modified the routine NVResizeMemory() to save the video memory size in the word variable POSTMemSize. In NVxx.ASM, modified the routine OEMRealMemSize() to read the memory size from the variable POSTMemSize. This fixed bug #60231. • InitScriptEngine() optimized. 4.18.20.08.00 • Changed FP_DDC_INITEDCB() to use the EDID already in the buffer @ FE00 if the first 16 bytes match the EDID read from the panel. This speeds up most set modes and flat panel enables (since we don’t change panels very often). • Added the ability to do partial EDID reads to GetEDID(). Added SetupI2C() routine that sets the video BIOS up on Head A with Head A controlling the I2C resources. • In OemIsModeAvailable(), removed the memory size check and replaced with a CLC. If we are passed the TV and LCD checks, it is assumed the mode is supported. • In OEMEnableFPEDCB(), no longer reprogram CR53/54 if the driver is loaded. This fixes Windows NT 4.0 bug #59744. • Added structure for selecting how many devices the video BIOS is POSTing to. 4.18.20.07.00 • BMP 5.19—Added byte that contains the maximum number of heads to use at POST. Default value is set to 2. Works in conjunction with previous word, which allowed disabling selectable DCBs from display enumeration at POST. This new test is performed afterwards. • Re-arranged PLL/PCLK power-up and power-down sequence to fix bug #56513. • Changed BMP version from 5.18 to 5.19. Changed to enable skipping selected DCBs from display enumeration at POST by checking a word of bit flags (the default value of the word is FFFFh, which allows all DCBs to be enumerated). Currently, this is only used by the video BIOS but drivers might use this in the future to POST displays on a non-primary adaptor. • Virtual Stack Version 3.0. This version provides • Safety checks to prevent more stack being used than the video BIOS was given on entry. • “Best Allocation Possible” swaps out as much stack as possible when the AllocVStack() call is made. • No more parameter passing to AllocVStack() and FreeVStack(). • Routines to save SP into the VStack and clear it. • Serial-out information for tracking VStack activity. • Reentrancy safety. • Also updated all calls to VStack to use new format. 4.18.20.05.00 • New chip-specific frequency band table definition files for PowerMizer tables. • Cut down VStack usage in TV path for Japanese DOS problem. • Check if KDA pointer valid at the beginning of AllocVStack() and FreeVStack(); fixes bugs #59930 and #59934. • Added code to the bmp_PostMemoryInitTbl table to clear the pointer to the KDA buffer. Fixes bug with video BIOS hanging in POST while reading invalid KDA data. 4.18.20.04.00 • Implementation of Virtual Stack 2.0. This version handles • nested calls to allocation and free routines correctly • checking page boundaries and stack underrun before allocating stack • Fixing an issue in Windows where the KDA buffer offset is overwritten by Windows “restoring” the A000 page during EDID read • Added code in the bmp_GenInitTbl to clear the KDA signature at 00720000h. During power cycling with Hynix memories, the KDA signature may still be intact. • Updated p111 drive/slew table and l18nz.rom DCB table. 4.18.20.03.00 • Increased KDA revision to 0x12 and checked in updated KDA document describing the new cell type 8. Cell types 4, 5, and 6 are also now allowed to appear in the production BIOS starting with this KDA revision. • Update CalcMNP() to use Virtual Stack to reduce total stack usage for DFPs during set modes. This fixes bug #58328. • Added Virtual Stack capability to the KDA Buffer tools. Routines AllocVStack() and FreeVStack() can be used to swap pages of stack (one page = 16 bytes) out to the KDA buffer. Also added LockKDA() and UnlockKDA() functions for locking the KDA buffer so the resource manager doesn’t move it while it is being used. • New drive/slew table for p111 added. • Placed mode2/3 and mode12 tables between other data to save ROM image space. • New ROM mask that doesn’t override external strapping for p111 boards added. • Added mode 2/3 table to let Korean Windows 98 switch from full-screen DOS window to normal. Fixes bug #57052. • Added the fix font routines into LoadUserFont(). When the system requests 8x14 fonts, even if it doesn’t have it, the BIOS now uses a fixed-up version of 8x16 that looks normal. Fixed bug # 56554. [Affected routine: FONT.asm—LoadUserFont()] • One more DAC-detection workaround: need to use CRT timing when doing CRT DAC detection. • Added check to see if chip was in DPMS state before disabling DPMS during a set mode. Since the chip is on most of the time SetMode() is called, this speeds up SetMode() and greatly reduces the stack it uses in most cases. • Cleaned up the stack usage in various I2C routines. Also, updated the specs of each routine. In addition to handling the one unnecessary push/pop edx in • Changed EDCBGetHeadDCBIndex() to return DCB index in AL and head in AH to match how most routines use that information. Removed all the xchg AH,AL code from routines calling EDCBGetHeadDCBIndex(). Also, cleaned up of OEMPostSetMode(). • Stack reduction changes made. • In SetMode(), changed the order of the screen-enabling routines, ATCOn() and FullCpuOff(), and OEMPostSetMode(). This fixes a brief corruption on screen. The OEMPostSetMode() takes an amount of time that made the corruption noticeable. Fixes bug #58276. [Affected routine: MODE.asm—SetMode()] • New set of functions for selective DPMS added. • Updated the head assignment after a display switch so it works as advertised: Broadcast mode is with head A primary unless • There is no device on head A. • There is a CRT on head B (and not on head A). If either is true, then broadcast is with head B primary. Also removed some old CR1A fix-up code that was commented out and no longer needed. • Rewrote portion of reduce_blanking_tweak() in order to shrink the stack size. This resolved the issue where Japanese DOS would not boot on the P70. [Affected routine: NV17.asm—reduce_blanking_tweak()] Fixed bug #58425.