Title: SII Specification Rev. 1.3 File: JAKE::USER$2:[FRAME.SII.DOC]SII.DOC Date: December 8, 1986 Author: Rob Frame SHR1-4/B10 DTN 237-2065 Abstract: This document describes the user requirements for the SII chip. This features high speed handling of the SCSI protocol through use of a DMA engine. Also featured is autonomous operation in DSSI mode. F O R I N T E R N A L U S E O N L Y Copyright ©1986 by Digital Equipment Corporation The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. This specification does not describe any program or product which is currently available from Digital Equipment Corporation nor does Digital Equipment Corporation commit to implement this specification in any program or product. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make. SII Spec. Rev 1.3 FOR INTERNAL USE ONLY Page ii Table of Contents 19 January 1987 CONTENTS 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 1 1.1 Goals . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Non-Goals . . . . . . . . . . . . . . . . . . . . 2 1.3 References . . . . . . . . . . . . . . . . . . . . 3 2 SCSI-II IN A MODULE . . . . . . . . . . . . . . . . 4 3 POSSIBLE CONFIGURATIONS . . . . . . . . . . . . . . 5 4 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . 7 5 SCSI-II INTERNAL REGISTERS . . . . . . . . . . . . 12 5.1 Register Definitions . . . . . . . . . . . . . . 19 5.1.1 SCSI Bus Registers . . . . . . . . . . . . . . 19 5.1.1.1 SDB - SCSI Data Bus . . . . . . . . . . . . 19 5.1.1.2 SC1 - SCSI Control Signals One . . . . . . . 19 5.1.1.3 SC2 - SCSI Control Signals Two . . . . . . . 20 5.1.1.4 CSR - Control/Status Register . . . . . . . 20 5.1.2 Bus Handling Registers . . . . . . . . . . . . 21 5.1.2.1 ID - Bus ID Register . . . . . . . . . . . . 21 5.1.2.2 SLCSR - Selector Control And Status Register 22 5.1.2.3 DESTAT - Selection Detector Status Register 22 5.1.2.4 DSTMO - DSSI Timeout Register . . . . . . . 23 5.1.3 Data Related Registers . . . . . . . . . . . . 24 5.1.3.1 DATA - Data Register . . . . . . . . . . . . 24 5.1.3.2 DMCTRL - DMA Control Register . . . . . . . 24 5.1.3.3 DMLOTC - DMA Length Of Transfer Counter . . 25 5.1.3.4 DMADDR - DMA Address Registers . . . . . . . 25 5.1.3.5 DMABYTE - DMA Initial Byte Register . . . . 25 5.1.3.6 STLP - Short Target List Pointer . . . . . . 26 5.1.3.7 LTLP - Long Target List Pointer . . . . . . 27 5.1.3.8 ILP - Initiator List Pointer . . . . . . . . 27 5.1.4 Command And Status Registers . . . . . . . . . 27 5.1.4.1 DSCTRL - DSSI Control Register . . . . . . . 28 5.1.4.2 CSTAT - Connection Status Register . . . . . 29 5.1.4.3 DSTAT - Data Transfer Status Register . . . 31 5.1.4.4 COMM - Command Register . . . . . . . . . . 33 5.1.5 Diagnostic And Test Registers . . . . . . . . 35 5.1.5.1 DICTRL - Diagnostic Control Register . . . . 35 5.1.5.2 CLOCK - Diagnostic Clock Register . . . . . 35 5.1.5.3 BHDIAG - Bus Handler Diagnostic Register . . 36 5.1.5.4 SIDIAG - SCSI IO Diagnostic Register . . . . 37 5.1.5.5 DMDIAG - Data Mover Diagnostic Register . . 38 5.1.5.6 MCDIAG - Main Control Diagnostic Register . 39 5.2 Register Initialization Values . . . . . . . . . 40 6 COMMANDS . . . . . . . . . . . . . . . . . . . . . 42 6.1 Immediate Commands . . . . . . . . . . . . . . 42 6.1.1 Chip Reset . . . . . . . . . . . . . . . . . . 42 6.1.2 Disconnect . . . . . . . . . . . . . . . . . . 42 6.2 Complex Commands . . . . . . . . . . . . . . . . 43 6.2.1 Request Data . . . . . . . . . . . . . . . . . 43 6.2.2 Select . . . . . . . . . . . . . . . . . . . . 43 6.2.3 Information Transfer Command . . . . . . . . . 44 7 SCSI MODE . . . . . . . . . . . . . . . . . . . . 46 7.1 Initiator Selection Of A Target . . . . . . . . 46 7.2 Initiator Selection With ATN Of A Target . . . . 47 SII Spec. Rev 1.3 FOR INTERNAL USE ONLY Page iii Table of Contents 19 January 1987 7.3 Target Reselection Of An Initiator . . . . . . . 47 7.4 Information Transfers . . . . . . . . . . . . . 48 7.4.1 Initiator Information Transfers . . . . . . . 48 7.4.1.1 DMA Operations . . . . . . . . . . . . . . . 48 7.4.1.2 Programmed I/O Transfers . . . . . . . . . . 49 7.4.2 Target Information Transfers . . . . . . . . . 50 7.4.2.1 DMA Operations . . . . . . . . . . . . . . . 50 7.4.2.2 Programmed I/O Transfers . . . . . . . . . . 52 7.5 Initiator Setting ATN . . . . . . . . . . . . . 52 7.6 SII Setting RST . . . . . . . . . . . . . . . . 53 7.7 Command Chaining . . . . . . . . . . . . . . . . 53 8 DSSI MODE . . . . . . . . . . . . . . . . . . . . 56 8.1 DSSI Bus Sequences . . . . . . . . . . . . . . . 56 8.2 Command Block Data Structure . . . . . . . . . . 58 8.3 Structures For Data . . . . . . . . . . . . . . 60 8.4 Linked List Operation . . . . . . . . . . . . . 61 8.5 Operation During DSSI Transfer . . . . . . . . . 63 8.5.1 Target Operations . . . . . . . . . . . . . . 64 8.5.2 Initiator Operations . . . . . . . . . . . . . 66 8.6 Adding To A Linked List . . . . . . . . . . . . 67 9 INTERNAL SUB-BLOCKS . . . . . . . . . . . . . . . 69 9.1 Bus Handler . . . . . . . . . . . . . . . . . . 69 9.2 SCSI Input/Output . . . . . . . . . . . . . . . 70 9.3 Data Mover . . . . . . . . . . . . . . . . . . . 70 9.4 II Block . . . . . . . . . . . . . . . . . . . . 71 9.5 Main Control . . . . . . . . . . . . . . . . . 72 10 BACK PORT MODES . . . . . . . . . . . . . . . . . 74 10.1 Back Port Mode 1 - (Phoenix Mode) . . . . . . . 74 10.1.1 Introduction . . . . . . . . . . . . . . . . . 74 10.2 Back Port Mode 2 - (Arbitrating Mode) . . . . . 74 10.2.1 Introduction . . . . . . . . . . . . . . . . . 74 10.2.2 Additional Functionality . . . . . . . . . . . 75 10.2.2.1 Memory Arbitration . . . . . . . . . . . . . 75 10.2.2.2 Address Counter Control . . . . . . . . . . 75 10.2.2.3 Reduced Address Capability . . . . . . . . . 75 11 TEST STRATEGY . . . . . . . . . . . . . . . . . . 76 11.1 Loop Back Testing . . . . . . . . . . . . . . . 76 11.2 Looped Connector Testing . . . . . . . . . . . . 76 11.3 Observation . . . . . . . . . . . . . . . . . . 76 12 EXTERNAL OPERATIONS AND TIMING . . . . . . . . . 78 12.1 Microprocessor Read Cycles . . . . . . . . . . . 78 12.2 Microprocessor Write Cycles . . . . . . . . . . 80 12.3 Memory Read Cycles (Normal Mode) . . . . . . . . 83 12.4 Memory Write Cycles (Normal Mode) . . . . . . . 85 12.5 Memory Read Cycles (Arbitrating Mode) . . . . . 87 12.6 Memory Write Cycles (Arbitrating Mode) . . . . . 89 13 IMPLEMENTATION GUIDELINES . . . . . . . . . . . . 92 APPENDIX A SII PINOUT SII Spec. Rev 1.3 FOR INTERNAL USE ONLY Page iv Table of Contents 19 January 1987 APPENDIX B DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE B.1 INTRODUCTION . . . . . . . . . . . . . . . . . . B-1 B.2 EXTERNAL LOOPBACK TESTING (LOOPED CONNECTOR) . . . B-1 B.3 INTERNAL LOOP AROUND TESTING . . . . . . . . . . . B-3 B.3.1 Target Testing . . . . . . . . . . . . . . . . . B-3 B.3.2 Initiator Testing . . . . . . . . . . . . . . B-13 APPENDIX C DATA LINK CODE - AN IMPLEMENTATION EXAMPLE C.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . C-1 C.1.1 Adding An Element Onto The ILP . . . . . . . . . C-1 C.1.2 Retries . . . . . . . . . . . . . . . . . . . . C-2 C.1.3 Receipt Of Incoming Traffic . . . . . . . . . . C-3 C.1.4 Reclaiming Of Allocated Buffers . . . . . . . . C-3 APPENDIX D APPLICATION CIRCUITS D.1 ARBITRATING MODE . . . . . . . . . . . . . . . . . D-1 D.2 NORMAL MODE . . . . . . . . . . . . . . . . . . . D-2 SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 1 Introduction 19 January 1987 1 INTRODUCTION This document is the user requirements specification for a general purpose, high speed, SCSI to II interface chip. The memory port of the proposed chip is modeled after the II (Integrated circuit Interconnect), which specifies a common protocol and interface timing to be used for inter-chip communication. This chip is tailored towards the new DSSI interconnect currently being developed. The proposed chip will be designed to optimize transfers when operating on a DSSI bus, at the expense of sophistication and complexity for the SCSI protocol. The intent of this document is to define, in detail, this user visible interface. This includes the memory interface signals and timing, the internal registers visible to the microprocessor through the memory interface, the various commands and the behavior of the chip during execution. 1.1 Goals The goals of the SII are simply stated and include: 1. Interface to the PHOENIX host port (in adapter master mode) without any "glue" logic (excepting passive devices). 2. Interface to any arbitrating memory through the host port with minimal "glue", i.e. make this a generic chip usable by several products. 3. To provide a backport interface which will facilitate interfacing to the local microprocessor with minimal "glue". 4. Support the SCSI specification for an arbitrating, multi-initiator SCSI bus with horizontal parity generation/checking using both asynchronous and synchronous data transfers. 5. Support both the initiator and target roles. 6. Allow the designer to create either a single-ended or a differential version of the SCSI bus. 7. Support programmable versions of some of the vendor unique features stated in the SCSI specification. 8. Implement commands complex enough to reduce the interrupt load on the attached microprocessor. 9. Implement synchronous data transfers at up to 4MB/s. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 2 Introduction 19 January 1987 10. The SII should use CMOS technology so as not to dissipate more than 0.8 watts. 11. The SII should be as inexpensive as possible (preferably standard cell with no more than 68 pins). 12. The SII should interface to the NCR 8310 Receiver/Driver Chip without any glue. 13. The SII should implement as much DSSI-specific functionality as possible. It should operate nearly autonomously in this mode (excepting error conditions). 1.2 Non-Goals 1. The SII need not be an autonomous component, handling the SCSI interface with no microprocessor intervention. Certain requirements of the SCSI protocol need not be met in the SII: 1. The SII need not drive the SCSI bus directly. 2. The SII need not support a non-arbitrating SCSI bus. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 3 References 19 January 1987 1.3 References Readers will find a working familiarity with the following documents essential to understanding the contents of this document: 1. SMALL COMPUTER SYSTEM INTERFACE (SCSI); Revision 17B (December 16, 1985) 2. PHOENIX HOST PORT SPECIFICATION; Revision 4.0 (September 12, 1986) 3. DSSA DATA LINK LAYER SPECIFICATION; Version V1.7 (October 31, 1986) SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 4 SCSI-II in a Module 19 January 1987 2 SCSI-II IN A MODULE The SII interfaces two "ports". One port is the memory backport. This includes sixteen multiplexed address/data lines along with two extra address lines, an address strobe, a data strobe, and a ready signal. This allows direct interface to the Phoenix chip, and also to easily interface to an arbitrated memory. This port will allow only address-data-data-data cycles. In other words, the address is present on the multiplexed address/data lines when the address strobe is asserted. Following this is a series of data strobes, each terminated by the receipt of a ready signal. These data strobes provide or expect data from sequential addresses in memory. There is also a second mode of operation for this port. It can be used on an arbitrated bus. In this case, the SII does the bus arbitration. HP_RDY becomes a bus request signal. In this mode, HP_AS is used as a counter clock and HP_ ADDR16 is used as a counter load. This port also allows a microprocessor to interface to the SII chip by utilizing the same multiplexed address/data lines, along with a chip select, an address enable and a data enable signal. Briefly, the SII will respond to the assertion of chip select by asserting the address enable output. At the deassertion of the signal, the SII will latch the address and direction of the transaction. Following that will be the data enable output. At the deassertion of this pulse, data will be latched by the SII on a write operation or will be available to the external device on a read operation. The second port is the SCSI/DSSI bus and the required control signals. The outputs from the SII are designed to interface directly with the NCR 8310 Receiver/Driver chip with no glue elements. The SII will generate and check parity and support both the initiator and target roles. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 5 Possible Configurations 19 January 1987 3 POSSIBLE CONFIGURATIONS Presently, there are three uses of the SII gate array: 1. RF70/30 disk drives The SII fits into the system as follows: +-----+ +-----+ +-----+ |68000| | ROM | | RAM | | | | | | | +-----+ +-----+ +-----+ +--------+--------+ V /-----\ +-----+ +-----+ / SCSI/ \| SII |<--->| PNX |<----> To Drive \ DSSI /| | | | Electronics \-----/ +-----+ +-----+ | V +-----+ | MEM | | | +-----+ In this case, the microprocessor communicates to the SII through the Phoenix (PNX) chip. All DMA transfers are directed to and from Phoenix memory. 2. KFQSA host adapters The SII fits into this system as follows: +-----+ +-----+ +-----+ | RAM | | ROM | |68000| | | | | | | +-----+ +-----+ +-----+ +--------+--------+ V +-----+ +-----+ /-----\ To Q-Bus <---->| FIFO|<->| SII |/ SCSI/ \ Interface | | | |\ DSSI / +-----+ +-----+ \-----/ | V +-----+ | MEM | | | +-----+ All DMA operations are directed through the FIFO into memory. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 6 Possible Configurations 19 January 1987 3. TF Tape Drives The SII fits into this system as follows: +-----+ +-----+ +-----+ | RAM | | ROM | |80186| | | | | | | +-----+ +-----+ +-----+ +--------+--------+ V +-----+ +-----+ /-----\ To Tape <---->| Bus |<->| SII |/ SCSI/ \ Interface | Ctrl| | |\ DSSI / +-----+ +-----+ \-----/ | V +-----+ | MEM | | | +-----+ The 80186 requests access to the buffer memory from the SII. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 7 Pin Description 19 January 1987 4 PIN DESCRIPTION To perform all of the required functions, the SII will have 68 pins, which will be in a PGA package. These pins can be easily divided into three categories. Two of these correspond to the ports previously mentioned, namely the SCSI port, and the memory port. The third is categorized as miscellaneous. This includes power pins, along with test and clock inputs. The pin descriptions are given below. All signals can be defined by one of the following signal types: o (BID) - Tri-State Bi-directional o (IN) - Input o (OUT) - Output o (OD) - Open Drain Output o (3S) - Tri-State SCSI port The SII interface to the SCSI drivers is composed of the following 28 signals: 1. SP_DATA<7:0> H. (BID). Unbuffered SCSI data bus (8 bits wide). 2. SP_PARITY H. (BID). Unbuffered SCSI parity line. 3. SP_CMD H. (BID). Unbuffered SCSI C/D line. 4. SP_MSG H. (BID). Unbuffered SCSI MSG line. 5. SP_SELIN H. (IN). SCSI SEL line, input. 6. SP_SELOUT H. (OUT, 3S). Unbuffered SCSI SEL line, output. 7. SP_INPUT H. (BID). Unbuffered SCSI I/O line. 8. SP_REQ H. (BID). Unbuffered SCSI REQ line. Attach a resistor to ground on this pin. 9. SP_ACK H. (BID). Unbuffered SCSI ACK line. Attach a resistor to ground on this pin. 10. SP_ARB H. (OUT, 3S). When asserted, arbitration is taking place and external hardware should assert this node's bit significant bus ID on the data lines. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 8 Pin Description 19 January 1987 11. SP_ATN H. (BID). Unbuffered SCSI ATN line. 12. SP_SBEN L. (OUT, 3S). When asserted, the SP_DATA and SP_PARITY lines should be asserted on the SCSI bus by external hardware. 13. SP_IGS H. (OUT, 3S). When asserted, the lines ACK and ATN should be driven on the SCSI bus (INITIATOR role only). 14. SP_TGS H. (OUT, 3S). When asserted, the MSG, CMD, REQ, and INPUT lines should be driven on the SCSI bus (TARGET role only). 15. SP_BSYIN H. (IN). Input SCSI BSY line. 16. SP_BSYOUT H. (OUT, 3S). Output SCSI BSY line, Unbuffered. 17. SP_RSTIN H. (IN). input SCSI RST line. This signal can also be used to signal the microprocessor that RST has been asserted on the SCSI bus. 18. SP_RSTOUT L. (OUT, 3S). Output SCSI RST line, Unbuffered. 19. SP_ID<2:0> L. (BID). The SCSI ID number, needed for input to the NCR 8310 Receiver/Driver chip. These represent the inversion of bits <2:0> in the ID register. These pins can be output from the SII or read by the SII, depending on the setting of a register bit. When the SYS_TEST pin is asserted, these pins determine which test mode the SII will enter. Memory Port The SII interface to the memory port is composed of the following 26 signals: 1. HP_DAL<15:00> H. (BID). Multiplexed address/data lines. During the data portion of the cycle, these signals represent DATA<15:00>. During the address portion, they are used to represent ADDRESS<15:01,17> (in arbitrating mode, ADDRESS<15:01,16>). This use of HP_DAL<00> during the address portion of the cycle doubles the space addressable by the SII. Contents of the bus may be determined by the assertion of the address and data strobes. 2. HP_ADDR16/HP_LOAD H. (OUT,3S). In normal mode, an extension of the address space addressable by the SII. Note that this and HP_DAL<00> allow the SII to access 256KB. This signal is used for address only and is SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 9 Pin Description 19 January 1987 valid only during the address portion of the bus cycle. In arbitrating mode, this signal is used as a load signal to an external counter. 3. HP_WRITE L. (BID). Asserted to indicate that the current cycle is a WRITE operation, as seen by the bus master, deasserted otherwise. When sourced by the external logic, it should be driven following the assertion of HP_ADREN L and may be released following the deassertion of HPADREN L; it must be released as late as following the deassertion of HP_AS. 4. HP_AS/HP_CTRCLK L. (OUT, 3S). In normal mode, defines the boundary of a cycle when asserted. Note that HP_DAL (containing an address) must be valid prior to the assertion of HP_AS (setup time for these signals, assertion edge of HP_AS is the latching condition). This signal will remain asserted for only the first transfer. This signal is also used during microprocessor accesses to the SII. Its deassertion is a signal to the external logic to stop driving HP_WRITE. In arbitrating mode, this signal is used as a clock input to an external counter. It is not asserted during microprocessor accesses in this mode. 5. HP_DS L. (OUT, 3S). Data strobe. Data must be present on HP_DAL<15:00> just after the assertion of HP_DS and is latched on the trailing edge by the SII on read cycles or by the memory on write cycles. This signal is used only when accessing memory. 6. HP_BUSGRANT L. (OUT, 3S). Bus Grant. The assertion of this signal indicates that the SII has relinquished the memory bus to another device. This signal is used only in arbitrating mode. 7. HP_RDY/HP_BUSREQ L. (IN). In normal mode, when asserted during the data portion of a memory cycle, it informs the SII that data is ready on a read operation or that data has been taken on a write operation and that the current cycle can end. This signal is not used during microprocessor accesses. In arbitrating mode, this signal is used as a bus request signal. The SII asserts HP_BUSGRANT in response to the assertion of this when it has relinquished the bus. 8. HP_CS L. (IN). This signal is asserted low to indicate that the local microprocessor wishes to access the SII. The SII will respond to this as soon as the current bus cycle (if one was in progress) has completed. This signal, together with the HP_WRITE signal will control the direction and enables of the transceivers in the chip. The HP_CS signal can be deasserted following the assertion of HP_ADREN. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 10 Pin Description 19 January 1987 9. HP_ADREN L. (OUT,3S). This signal is asserted in response to a chip select to inform the local microprocessor that the register address may be placed on the HP_DAL lines. This signal can also act as a bus grant to the microprocessor. The local intelligence will also drive HP_WRITE following the assertion of this signal. This signal is not used during memory accesses. 10. HP_DATAEN L. (OUT,3S). This signal is asserted when the SII is ready to accept or deliver data on the HP_DAL lines. This signal, coupled with HP_WRITE can act as the enable and direction inputs to an external transceiver. This signal is not used during memory accesses. 11. HP_CLK H. (IN). This is the clock input used by the SII to synchronize HP_CS,HP_ADREN and HP_DATAEN. This allows the designer to use synchronous circuitry, if desired. If not, this pin may be connected to SYS_CLK. Miscellaneous The SII also requires a few interface connections on its own behalf. These 14 signals are: 1. SYS_INT L. (OUT,OD). One multi-purpose interrupt line to the local microprocessor to inform it of termination or error conditions. Its assertion indicates that an interrupt is pending. 2. SYS_RESET L. (IN). This signal, when asserted, will cause the SII chip to reset all internal state machines, initialize all registers and disconnect itself from the SCSI bus. 3. SYS_CLK H. (IN). This is the clock input for the SII. Supply a 20 MHz, 50% duty cycle clock. 4. SYS_TEST L. (IN). Pull up this pin for normal operation. When pulled low, the SII is in test mode. When in this mode, the SP_ID bits determine the operation of the SII: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 11 Pin Description 19 January 1987 SPID<2> SPID<1> SPID<0> Function +-------+-------+-------+-------------------------------+ | 0 | 1 | 1 | Tri-state SII outputs | | | | | | | 1 | 0 | 1 | Enables parametric outputs | | | | | used for ASIC specific testing| | | | | | | 1 | 1 | 0 | Allows access to 2 adjacent | | | | | registers. (SPID<0> is least | | | | | significant address bit in | | | | | test mode.) | +-------+-------+-------+-------------------------------+ None of these modes should be entered in normal operation. 5. VDD<3:0>. (IN). These are the 4 power lines to the SII. Supply +5V +/-5%. 6. GND<5:0>. (IN). These are the 6 ground lines to the SII. NOTE All signals noted as bidirectional use tri-state drivers. All signals noted as output also use tri-state drivers. These output-only signals become tri-state when the TEST input is asserted, along with SP_ID<2>. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 12 Pin Description 19 January 1987 Pin Summary _______________________________________ | | | SCSI Port | | | <======>| SP_DATA<7:0> SP_SELOUT |------> <------>| SP_PARITY SP_ARB |------> <------>| SP_CMD SP_SBEN |O-----> <------>| SP_MSG SP_IGS |------> ------->| SP_SELIN SP_TGS |------> <------>| SP_INPUT SP_BSYOUT |------> <------>| SP_REQ SP_RSTOUT |O-----> <------>| SP_ACK SP_ID<2:0> |O<====> <------>| SP_ATN | ------->| SP_BSYIN | ------->| SP_RSTIN | | | |_______________________________________| | | | Memory Port | | | <======>| HP_DAL<15:00> HP_AS/CTRCLK |O-----> <-------| HP_ADDR16/LOAD HP_DS |O-----> <----->O| HP_WRITE HP_BUSGRANT |O-----> ------>O| HP_RDY/HP_BUSREQ HP_ADREN |O-----> ------>O| HP_CS HP_DATAEN |O-----> ------->| HP_CLK | | | |_______________________________________| | | | Miscellaneous | | | ------>O| SYS_RESET SYS_INT |O-----> ------->| SYS_CLK | ------->| SYS_TEST | =======>| VDD<3:0> | =======>| GND<5:0> | | | |_______________________________________| 5 SCSI-II INTERNAL REGISTERS The SII contains twenty-seven microprocessor-visible registers that are used to control and monitor the behavior of the SII during operation. Four of these registers provide direct control of the SCSI bus for diagnostic testing. Six additional registers provide more visibility into the SII. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 13 SCSI-II Internal Registers 19 January 1987 Four of these registers controls the SII handling of the SCSI bus. These registers contain information regarding SCSI selection and selection detection. Nine registers are used to control the data movement and the DMA engine inside the SII. Four registers provide exception notification information, error flags, and control of the SII in a global sense. The register "map" is defined below: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 14 SCSI-II Internal Registers 19 January 1987 SII REGISTER MAP (USER VISIBLE) HP__DAL<5:0> DATA BUS NAME 15 0 +-------------------------------+ +00 | SCSI DATA BUS AND PARITY | SDB +-------------------------------+ +02 | SCSI CONTROL SIGNALS 1 | SC1 +-------------------------------+ +04 | SCSI CONTROL SIGNALS 2 | SC2 +-------------------------------+ +06 | CONTROL/STATUS REGISTER | CSR +-------------------------------+ +08 | ID REGISTER | ID +-------------------------------+ +10 | SELECTOR CONTROL/STATUS | SLCSR +-------------------------------+ +12 | SELECTION DETECTOR STATUS | DESTAT +-------------------------------+ +14 | DSSI TIMEOUTS | DSTMO +-------------------------------+ +16 | DATA REGISTER | DATA +-------------------------------+ +18 | DMA CONTROL REGISTER | DMCTRL +-------------------------------+ +20 | DMA LENGTH OF TRANSFER | DMLOTC +-------------------------------+ +22 | DMA ADDRESS POINTER | DMADDRL +-------------------------------+ +24 | DMA ADDRESS POINTER | DMADDRH +-------------------------------+ +26 | DMA INITIAL BYTE | DMABYTE +-------------------------------+ +28 | SHORT TARGET LIST POINTER | STLP +-------------------------------+ +30 | LONG TARGET LIST POINTER | LTLP +-------------------------------+ +32 | INITIATOR LIST POINTER | ILP +-------------------------------+ +34 | DSSI CONTROL | DSCTRL +-------------------------------+ +36 | CONNECTION INTERRUPT CONTROL| CSTAT +-------------------------------+ +38 | DATA INTERRUPT CONTROL | DSTAT +-------------------------------+ +40 | COMMAND REGISTER | COMM +-------------------------------+ +42 | DIAG. CONTROL REGISTER | DICTRL +-------------------------------+ +44 | CLOCK REGISTER | CLOCK +-------------------------------+ +46 | BH DIAG REGISTER | BHDIAG +-------------------------------+ SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 15 SCSI-II Internal Registers 19 January 1987 +-------------------------------+ +48 | SCSI_IO DIAG REGISTER | SIDIAG +-------------------------------+ +50 | DM DIAG REGISTER | DMDIAG +-------------------------------+ +52 | MC DIAG REGISTER | MCDIAG +-------------------------------+ SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 16 SCSI-II Internal Registers 19 January 1987 The registers of the SII can be divided into several categories according to usage. These categories can be described as: Diagnostic - those registers which are used ONLY to diagnose the functionality of the chip and nearby circuitry. Typically, these registers are accessed only during power-up testing. SCSI - those registers which are used when the SII is operating in SCSI mode. These registers are also used internally by the SII while in DSSI mode; however, there is no need for the user to access them in this mode. DSSI - those registers which are used only in DSSI mode. Typically, these registers contain addresses where information regarding DSSI operation can be found. Other registers may be accessed while in this mode; however, the information contained in them can be found elsewhere (typically in memory). Most registers in the SII are standard read/write registers. Some, however, do not fall into this class. These other classes are: R/W1TC - read/write 1 to clear. Several status registers contain bits which require that once a status bit has been set, it can only be cleared by writing a 1 to that bit position. R/O - read only. Several status registers contain only status and writing to them has no effect. W/O - write only. The clock register is only an address location. It is not implemented as a register and will always read zero. R/W* - these registers are not true read/write in that under certain conditions they will not read back the value last written to them. These conditions will be noted in the description of the register. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 17 SCSI-II Internal Registers 19 January 1987 SII REGISTER MAP NAME USAGE CLASS +---------------+---------------+---------------+ | SDB | DIAGNOSTIC | R/W* | +---------------+---------------+---------------+ | SC1 | DIAGNOSTIC | R/W* | +---------------+---------------+---------------+ | SC2 | DIAGNOSTIC | R/W* | +---------------+---------------+---------------+ | CSR | SCSI/DSSI | R/W | +---------------+---------------+---------------+ | ID | SCSI/DSSI | R/W* | +---------------+---------------+---------------+ | SLCSR | SCSI | R/W | +---------------+---------------+---------------+ | DESTAT | SCSI | R/O | +---------------+---------------+---------------+ | DSTMO | DSSI | R/W | +---------------+---------------+---------------+ | DATA | SCSI | R/W* | +---------------+---------------+---------------+ | DMCTRL | SCSI | R/W | +---------------+---------------+---------------+ | DMLOTC | SCSI | R/W | +---------------+---------------+---------------+ | DMADDRL | SCSI | R/W | +---------------+---------------+---------------+ | DMADDRH | SCSI | R/W | +---------------+---------------+---------------+ | DMABYTE | SCSI | R/W | +---------------+---------------+---------------+ | STLP | DSSI | R/W | +---------------+---------------+---------------+ | LTLP | DSSI | R/W | +---------------+---------------+---------------+ | ILP | DSSI | R/W | +---------------+---------------+---------------+ | DSCTRL | DSSI | R/W | +---------------+---------------+---------------+ | CSTAT | SCSI/DSSI | R/W1TC | +---------------+---------------+---------------+ | DSTAT | SCSI | R/W1TC | +---------------+---------------+---------------+ | COMM | SCSI | R/W | +---------------+---------------+---------------+ | DICTRL | DIAGNOSTIC | R/W | +---------------+---------------+---------------+ | CLOCK | DIAGNOSTIC | W/O | +---------------+---------------+---------------+ | BHDIAG | DIAGNOSTIC | R/W,R/O | +---------------+---------------+---------------+ | SIDIAG | DIAGNOSTIC | R/O | +---------------+---------------+---------------+ SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 18 SCSI-II Internal Registers 19 January 1987 +---------------+---------------+---------------+ | DMDIAG | DIAGNOSTIC | R/O | +---------------+---------------+---------------+ | MCDIAG | DIAGNOSTIC | R/O | +---------------+---------------+---------------+ NOTE For the entirety of the document, please keep in mind that all memory references are made with BYTE addresses. Note that the maximum address size of 18-bits restricts the amount of memory visible to the SII to 256K bytes. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 19 SCSI-II Internal Registers 19 January 1987 5.1 Register Definitions NOTE All undefined bits in any registers will read as zero (0). Writing to any of these bits will have no effect. 5.1.1 SCSI Bus Registers This group of registers are closely associated with the SCSI bus. Several are diagnostic registers used to control the SCSI bus and the remaining register is used to control the operation of the chip with respect to the SCSI bus. 5.1.1.1 SDB - SCSI Data Bus The SDB register is used only in diagnostic mode (see DICTRL description) in conjunction with a loop back connector to test the SCSI port. It is also used in diagnostic internal loopback mode to effectively act like the SCSI bus. The fields in this register directly reflect the SCSI data bus ASSERTED HIGH. This register should NOT be used during normal operations. It should be noted that care must be taken to test this portion of the chip without any disturbance to the SCSI bus. (See TEST STRATEGY) SDB (0) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - |PTY| SP DATA <7:0> | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.1.2 SC1 - SCSI Control Signals One This register is used in diagnostic mode (see DICTRL description) in conjunction with a loop back connector to test the SCSI port or to effectively act as the SCSI bus in internal loopback mode. The bits in this register directly reflect some of the SCSI control lines ASSERTED HIGH. It should be noted that data written to this register may differ from that read back since only certain bits are driven while in the target or initiator mode. (See TEST STRATEGY) SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 20 SCSI-II Internal Registers 19 January 1987 SC1 (2) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - |BSY|SEL|RST|ACK|REQ|ATN|MSG|C/D|I/O| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.1.3 SC2 - SCSI Control Signals Two The SC2 register is used only in diagnostic mode (see DICTRL description) in conjunction with a loop back connector to test the SCSI port. These signals directly drive the four control signals on the NCR 8310 receiver/driver chip. Special care should be taken when writing this register to avoid disturbing the SCSI bus during power-up diagnostics. This register should only be accessed if an external loop-back connector is in plase. It should not be used during normal operations. (See TEST STRATEGY) SC2 (4) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - | - |IGS|TGS|ARB|SBE| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ o IGS - is set (1) to steer the SCSI drivers for the initiator role. READ/WRITE. o TGS - is set (1) to steer the SCSI drivers for the target role. READ/WRITE. o ARB - is set (1) to enable the SCSI drivers for arbitration. READ/WRITE. o SBE - is set (1) to drive the SCSI data bus and parity lines. READ/WRITE. 5.1.1.4 CSR - Control/Status Register This register contains control and status information about the general operation of the SII in regard to the SCSI bus, including various enable bits. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 21 SCSI-II Internal Registers 19 January 1987 CSR (6) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - |HPM|RSE|SLE|PCE| IE| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The fields in the CSR are defined as follows: o HPM - set to one (1) if the SII is operating on an arbitrated bus. In this mode, the SII will handle the arbitration. HP_RDY is used as a BUS_REQ, the SII returns HP_BUSGRANT to indicate that the external device has control of the bus. When clear(0), HP_RDY acts as an indicator that the current data transfer can be terminated and HP_BUSGRANT is not used. o RSE - set to one (1) if the SII is to respond to reselections. Clear (0) (default on reset) otherwise. o SLE - set to one (1) if the SII is to respond to selections. Clear (0) (default on reset) otherwise. o PCE - set to one (1) if the SII is to check parity and report parity errors. When clear (0), the SII will continue to check parity but will not report any errors. In either case, the SII will continue to generate parity. The default value is zero (0). o IE - set to one (1) if interrupts are to be enabled. Clear (0) (the default on reset) otherwise. If clear, all interrupts are disabled. 5.1.2 Bus Handling Registers This group of registers handle and monitor the SCSI/DSSI bus. These registers provide information regarding selection and selection detection, required by the SII. A fourth register is used to monitor DSSI transactions, insuring that the bus does not become "hung". 5.1.2.1 ID - Bus ID Register This register contains the three bit ID number of this SII on the SCSI/DSSI bus. This value is needed for selection and selection detection. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 22 SCSI-II Internal Registers 19 January 1987 ID (8) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |I/O| - | - | - | - | - | - | - | - | - | - | - | - | BUS ID | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits is this register are defined as follows: o I/O - when set to one, indicates that the 3 ID pins of the SII are outputs and the values presented in the ID register are reflected (complemented) at these pins. It is expected that this register be written before the SII is enabled. When clear, the ID pins are inputs. The logical inversion of these pins will appear in the ID register. Note that if this bit is cleared, writing this register has no effect. o BUS ID - the ID of the SII. 5.1.2.2 SLCSR - Selector Control And Status Register SLCSR (10) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - | - | - | BUS ID | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o BUS ID - the ID of the device to be selected or reselected (destination ID). This must be loaded before a SELECT command is issued. 5.1.2.3 DESTAT - Selection Detector Status Register This register contains the bus ID of the device which has selected the SII. It is typically read after an interrupt is received to dispatch to the ID-dependent code. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 23 SCSI-II Internal Registers 19 January 1987 DESTAT (12) -- READ ONLY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - | - | - | BUS ID | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o BUS ID - the number of the device which selected the SII (source ID). This register is only updated by the SII after being selected. 5.1.2.4 DSTMO - DSSI Timeout Register This register contains the timeout values for both the initiator and target roles. Also contained is a single enable bit. Note that once enabled, the timeout values apply to all transactions. DSTMO (14) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |ENA| - | - | - | - | - | - | - |TARGET TIMEOUT |INIT. TIMEOUT | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o ENA - when set to one (1), indicates the timeout values placed on bus transactions apply and that necessary action should be taken if either of these timers expires. When clear (0), (default on reset) these timeouts are ignored. o TARGET TIMEOUT - the number of 200 microsecond intervals which may elapse, starting from the point when the SII was selected until the next observed bus free phase while the SII is in the target role. Should this timer expire, the SII will immediately disconnect from the DSSI bus. o INITIATOR TIMEOUT - the number of 200 microsecond intervals which may elapse, from the last observed bus free phase, until the next observed bus free phase while the SII is in the initiator role; or the number of 200 microsecond intervals which may elapse before the SII, acting as a potential initiator, detects a bus free phase. Should either of these conditions occur, the SII will assert SCSI bus reset. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 24 SCSI-II Internal Registers 19 January 1987 5.1.3 Data Related Registers There are several registers necessary to control and report the status of data movement within the SII. Many of these deal with the DMA engine contained in the SII. These registers control the DMA operations to and from memory. Included in this group is a control register, several address pointers and length counter register. 5.1.3.1 DATA - Data Register This register is used to load data to be sent out on the SCSI bus. It can also be used to read incoming information. Typically, it would be used for message and status phases. For all programmed I/O operations, only the lower byte is used. This register cannot be used for synchronous data transfers. This register will not reflect the data written to it. DATA (16) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | LOWER BYTE | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.3.2 DMCTRL - DMA Control Register This register contains mode information concerning the current DMA activity. This consists of the req/ack offset used for synchronous data transfers. Note that this register must be written following detection of a selection or reselection to insure proper operation during synchronous data transfers. In DSSI mode, the register is loaded automatically by the SII. DMCTRL (18) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |REQ/ACK| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ These bits are defined as follows: o REQ/ACK OFFSET - the desired request/acknowledge offset for any synchronous data transfers occurring during this connection. A maximum of three (3) is implemented for data phase transfers. A zero (0) value implies SCSI asynchronous data transfers. This offset is only for data phase transfers; other information phases must be done asynchronously. It should be noted that there is no special SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 25 SCSI-II Internal Registers 19 January 1987 command for synchronous data transfer. A non-zero value for the REQ/ACK offset implies all data transfers are done in synchronous mode. 5.1.3.3 DMLOTC - DMA Length Of Transfer Counter This register contains the number of BYTES which are to be DMA'ed into/out of memory. This register will auto-decrement after each transaction and will reflect the number of bytes left to transfer. It will be implemented as a 13 bit counter. This register will contain the number of bytes sent across the SCSI bus during a read and the number of bytes deposited into RAM on a write. This is a true count and bytes currently in the FIFO are not considered transferred. DMLOTC (20) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | TRANSFER COUNT ( IN BYTES) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.3.4 DMADDR - DMA Address Registers This register contains the memory byte address from which the DMA operation will begin. Note that a "1" in the least significant bit position means that the first cycle will be done with an initial byte offset. DMADDRL (22) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | BYTE ADDRESS FOR DMA OPERATION | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ DMADDRH (24) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ADDR | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.3.5 DMABYTE - DMA Initial Byte Register This register is used to load data to be sent to the memory bus. Typically, it would be used in the following scenario: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 26 SCSI-II Internal Registers 19 January 1987 o The SII is operating as an initiator o The target is sending data to this SII. o The target changes phase on an odd boundary and requests the pointers be saved. o The SII interrupts the microprocessor indicating a phase change has occurred and the DMA transfer ended on an odd byte boundary. o At some later time, the target reconnects to complete the transfer. o The microprocessor will load the "odd" byte from the previous transfer into this register. o After receiving the next byte, the SII will transfer the whole word into memory. DMABYTE (26) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | INITIAL BYTE | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.3.6 STLP - Short Target List Pointer This register contains the address to which the SII will write the next incoming short packet. The SII will automatically reload this register with its new value upon completion of the current transaction. Refer to DSSI MODE description. Note that this address is really an 18-bit byte address, with the lower three bits of the address forced to zero (0). The register contains the upper fifteen bits of this 18-bit address. The SII will interpret a value of zero (0) as the end of a linked list. This register can only be written by the microprocessor when the register is zero or DSSI_EN (in DSCTRL register) is zero. All other attempts to write this register will be ignored. STLP (28) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ADDRESS OF NEXT FREE "INCOMING" SHORT BUFFER | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 27 SCSI-II Internal Registers 19 January 1987 5.1.3.7 LTLP - Long Target List Pointer This register contains the address to which the SII will write the next incoming long packet. The SII will automatically reload this register with its new value upon completion of the current transaction. Refer to DSSI MODE description. Note that this address is really an 18-bit byte address, with the lower three bits of the address forced to zero (0). The register contains the upper fifteen bits of this 18-bit address. The SII will interpret a value of zero (0) as the end of a linked list. This register can only be written by the microprocessor when the register is zero or DSSI_EN (in DSCTRL register) is zero. All other attempts to write this register will be ignored. LTLP (30) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ADDRESS OF NEXT FREE "INCOMING" LONG BUFFER | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.3.8 ILP - Initiator List Pointer This register contains the address from which the SII will read the next outgoing packet. The SII will automatically reload this register with its new value upon successful completion of the current transaction. Refer to DSSI MODE description. The SII will interpret a value of zero (0) as the end of a linked list. Note that this address is really a 18-bit byte address, with the lower three bits of the address forced to zero (0). The register contains the upper fifteen bits of this 18-bit address. This register can only be written by the microprocessor when the register is zero or OUT_EN (in DSCTRL register) is zero. All other attempts to write this register will be ignored. ILP (32) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ADDRESS OF NEXT FULL "OUTGOING" BUFFER | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.4 Command And Status Registers The registers in this group provide for global control of the SII. Several provide status information to the local microprocessor regarding the state of the SII. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 28 SCSI-II Internal Registers 19 January 1987 5.1.4.1 DSCTRL - DSSI Control Register This register contains all necessary information to control the SII in DSSI mode. Included in this register is information about the nature of each node, whether it is a SCSI or DSSI device. DSCTRL (34) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |DSI|OUT| - | - | - | - | - | - |CH7|CH6|CH5|CH4|CH3|CH2|CH1|CH0| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o DSI - (DSSI_EN) when set to one (1), indicates that the SII is acting in DSSI mode. This bit must be set by the microprocessor. It is cleared by the SII if: 1. it is selected by non-DSSI device 2. it is selected with Attention 3. it selects a non-DSSI device Care must be taken if the microprocessor wishes to clear this bit. Deasserting this bit in the middle of a transfer will cause unexpected results. The recommended method of clearing this bit is as follows: 1. Clear all of the channel bits. This way, the chip will not attempt to transfer any more packets following the current one (if one is in progress). 2. The next time the SII is selected or attempts to process an outbound element, this bit will be cleared. 3. If the time required to wait for the above action to occur is too great, the code may poll a diagnotic register (MCDIAG) until it reads 0100H. At this time, it is safe to clear the DSI bit. After the microprocessor has finished servicing any of the above conditions, it must set this bit to one again to resume DSSI operation. It is advisable that the firmware raise its interrupt priority level prior to the disconnect so that the setting of this bit is guaranteed to be done immediately. o OUT_EN - when set to one (1), this indicates the SII is enabled to send outbound packets. This bit must be set by the microprocessor. It is cleared by the SII if: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 29 SCSI-II Internal Registers 19 January 1987 1. ILP becomes zero 2. DSTMO occurs 3. An outbound transaction is not terminated with ACK. The code is free to clear this bit whenever it deems it necessary with no unexpected effects. o CHn - when set to one (1), this indicates that the specified node is operating as a DSSI device. When clear (0) (the default on reset), the node is assumed to be a SCSI device. The SII uses this information to determine its course of action when selected by a device. It will interrupt the microprocessor if selected by a SCSI device. If selected by a DSSI device, it will proceed through the DSSI mode sequence. The code is free to clear any of these bits whenever it deems it necessary with no unexpected effects. 5.1.4.2 CSTAT - Connection Status Register This register contains interrupt status related to SII connections. CSTAT (36) -- READ/SELECTIVE WRITE 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |CI |DI |RST|BER|OBC|TZ |BUF|LDN|SCH|CON|DST|TGT|SWA|SIP|LST| 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ * * * * * * These bits are defined as follows: o CI - CSTAT Interrupt - composite error bit for the CSTAT register. It is the logical 'or' of bits 13 through 11 and 9 through 7. Those bits marked by '*' will interrupt the processor when set. o DI - DSTAT Interrupt - composite error bit for the DSTAT register. o RST - RST asserted - set to one (1) if the RSTIN signal is asserted on the SCSI bus. The SII will automatically disconnect itself from the bus and interrupt the processor. This bit is write one (1) to clear. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 30 SCSI-II Internal Registers 19 January 1987 o BER - Bus Error - this bit is set on any of the following conditions: 1. Fifo Overflow 2. Req/Ack Offset exceeded 3. Illegal Phase change While this bit is asserted, the SII will not receive or transmit data in either DMA or programmed I/O mode. This bit is write one (1) to clear. o OBC - Out_en Bit Cleared - this bit is set to one (1) if (in DSSI mode): 1. The SII has received RSTIN 2. The SII DSSI timer has expired 3. As an initiator, the attached target disconnects unexpectedly. This bit is write one (1) to clear. o TZ - Target pointer Zero - this bit is set to one (1) if the STLP register or the LTLP register contains a value of 0. (Read only) o BUF - Buffer Service - this bit is set to one (1) if the SII has begun processing an outbound packet destined for a non-DSSI device. Write one (1) to clear this bit. o LDN - List Element Done - this bit is set to one (1) if the SII has completed an element, successfully or not, with interrupt enabled. Write one (1) to clear this bit. o SCH - State Change - this bit is set to one (1) if the state of the SII has changed. A change is considered to be any of the following: 1. Selected (while in non-DSSI mode) 2. Reselected (while in non-DSSI mode) 3. Disconnected (while in non-DSSI mode) 4. RST has occurred on the SCSI bus (while in non-DSSI mode) 5. The SII leaves DSSI mode - DSSI_EN is cleared by the SII (see DSCTRL register) SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 31 SCSI-II Internal Registers 19 January 1987 Write one (1) to clear this bit. o CON - Connected - this bit is set to one (1) if the SII is connected to another device. It is clear while the SII is idle. (Read only) o DST - Destination - this bit is set to one (1) if the SII was the destination of the current transfer. In other words, this bit is set if the SII was selected or reselected by another device. (Read only) o TGT - Target - this bit is set to one (1) if the SII is operating as a target during the current transfer. (Read only) o SWA - Selected With ATN - this bit is set to one if the SII was selected with attention. Write one (1) to clear this bit. o SIP - Selection In Progress - this bit is set if the SII is currently in a selection process. This is useful in determining if the desired destination is unavailable. (Read only) o LST - Lost - this bit is set when the SII loses arbitration. It is cleared by the SII when it begins a selection process. (Read only) 5.1.4.3 DSTAT - Data Transfer Status Register This register contains interrupt status related to data transfers. DSTAT (38) -- READ/SELECTIVE WRITE 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |CI |DI |DNE|TCZ|TBE|IBF|IPE|OBB| 0 | 0 | 0 |MIS|ATN|MSG|C/D|I/O| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ * * * * These bits are defined as follows: o CI - CSTAT Interrupt - composite error bit for the CSTAT register. o DI - DSTAT Interrupt - composite error bit for the DSTAT register. It is the logical 'or' of bits 13,11,10 and 4. Those bits marked with '*' will interrupt the processor when set. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 32 SCSI-II Internal Registers 19 January 1987 o DNE - Xfer Done - this bit is set to one (1) when the DMA operation is completed (successfully or not). This bit is write one (1) to clear. o TCZ - Transfer Counter Zero - this bit is set when the transfer counter has a value of zero. Cleared otherwise. o TBE - Transmit Buffer Empty - This bit is set to one (1) if the attached target requests data from the SII while there is no command pending for the datamover (i.e. an Info Xfer command is not in progress). This bit is cleared when an Info Xfer command is started (either DMA or programmed I/O). o IBF - Input Buffer Full - this bit is set to one (1) if the SII has received a byte while there is no command pending for the datamover (i.e. an Info Xfer command is not in progress). This bit is cleared when an Info Xfer command is started (either DMA or programmed I/O). o IPE - Incoming Parity Error - this bit is set to one (1) if there was a parity error on the incoming data. It remains asserted until the next DMA operation begins. o OBB - Odd Byte Boundary - this bit is set if the current transfer has ended on an odd byte boundary. It is automatically reset by the SII when the next DMA operation begins. This can be used in conjunction with the previous register to solve "odd byte disconnects". o MIS - Phase Mismatch - this bit is set to one (1) if the phase currently on the bus does not match the expected phase (as described in the COMM register) and a REQ has been issued by the target. This bit should only be asserted while acting in the initiator role. This bit is cleared by resolving the difference in phase by modifying the COMM register. o ATN - this bit is set to one (1) if, while the SII was in the target role, the initiator asserted ATN. Write one (1) to clear this bit. o C/D - set to one (1) if the current bus state has the C/D signal asserted. This bit is read only. o MSG - set to one (1) if the current bus state has the MSG signal asserted. This bit is read only. o I/O - set to one (1) if the current bus state has the I/O signal asserted. This bit is read only. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 33 SCSI-II Internal Registers 19 January 1987 5.1.4.4 COMM - Command Register The SII uses this register to determine its actions while operating in SCSI mode. This register also contains information concerning use of DMA in the present command. This register is ignored by the SII in DSSI mode and therefore should not be used by the microprocessor in that mode. COMM (40) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |DMA|RST| 0 |RSL| COMMAND |CON|ORI|TGT|ATN|MSG|C/D|I/O| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o DMA - when asserted, data will be transferred to and from the memory area. When clear, data will be sent and received via the microprocessor through the DATA register. o RST - when written to one (1), the SII will assert RST on the SCSI/DSSI bus for 25 µsec. This bit always reads zero. o RSL - when asserted (1) along with a SELECT command, the SII will attempt to reselect the desired device. When clear (0), the SII will attempt a selection. o COMMAND<4:0> - these bits, collectively, control the actions of the SII. The roles in which these commands are valid are listed parenthetically. o I - initiator role o T - target role o D - disconnected These bits are defined in the following manner: - 00001 - Chip Reset - (I,T,D) - This command resets the entire chip in the same manner as a "hard" reset. - 00010 - Disconnect - (I,T,D) - This command forces the SII to release all signals it is driving on the SCSI bus (as a target). It is also used to "gracefully" abort a selection/ reselection attempt. NOTE The disconnect bit should not be written to one (1) if the SII is already disconnected. The command will remain in the COMM register and SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 34 SCSI-II Internal Registers 19 January 1987 cause the SII to disconnect immediately following the next time it is selected. - 00100 - Request Data - (T) - This command forces the SII to issue a REQ on the SCSI bus. This command must be used only while a target receiving data. In order for this command to be executed, bits <6:3> of the COMM register must match bits <6:3> of the CSTAT and bits <2:0> of the COMM register must match bits <2:0> of the DSTAT register. - 01000 - Select - (D) - This command allows the SII to attempt to select or reselect another device on the bus. - 10000 - Information Transfer - (I,T) - This command allows the SII to transfer information to and from another device. This command is only valid while connected to another device. In order for this command to be executed, bits <6:3> of the COMM register must match bits <6:3> of the CSTAT and bits <2:0> of the COMM register must match bits <2:0> of the DSTAT register. NOTE The information transfer bit is only cleared by clearing the command or a DONE interrupt. It is not cleared when the SII becomes disconnected from the bus or when RSTIN is asserted. o State lines - (D,I,T) - These three bits make up the expected state of the chip. These bits must match those in the CSTAT register for a data transfer to take place. These bits are: 1. CON - Connected 2. DST - Destination 3. TGT - Target o SCSI control lines - (I,T) - This is used to directly drive several of the bus signals. While in SCSI mode and acting as a target, the values written to C/D,I/O, and MSG are driven onto the SCSI bus. While acting as an initiator, ATN is driven onto the SCSI bus. In either mode, the bits constitute the "expected phase". The three phase bits must match those on the SCSI bus or MIS is set in the DSTAT register (following receipt of a REQ from the target). SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 35 SCSI-II Internal Registers 19 January 1987 5.1.5 Diagnostic And Test Registers This group of registers is used specifically and only for test and diagnostic purposes. They should never be used while in normal operation. 5.1.5.1 DICTRL - Diagnostic Control Register This register contains the various control bits used in diagnostic mode. DICTRL (42) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - | - |LPB|PRE|DIA|TST| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits is this register are defined as follows: o LPB - set to one (1) if the values written to the diagnostic registers are to be looped back into the chip. This will enable the microprocessor to insert test vectors into the chip during power-up diagnostics if desired. Note that the DIA bit must be deasserted for this test to be meaningful. Clear (0) (default on reset) otherwise. Refer to TEST STRATEGY. o PRE - port enable. Set to one (1) to enable the off-chip drivers to the SCSI port. After a reset, the SII will be disconnected from the bus (this bit will be zero). The primary purpose of this bit is to allow chip diagnostics to run without affecting the rest of the SCSI/DSSI bus. o DIA - When this bit is asserted, the SII is in external loop-back mode. In this mode, the diagnostic registers directly control the SCSI data and control lines, as well as the bus steering signals. After a RESET condition, this bit is zero (0). Refer to TEST STRATEGY. o TST - is set to one (1), when the chip is in test mode. This enables the user to replace the 20 MHz clock. The new clock is pulsed each time the CLOCK register is written. 5.1.5.2 CLOCK - Diagnostic Clock Register Writing this register generates a pulse which, in test mode, replaces the 20 MHz clock input. Note this register must SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 36 SCSI-II Internal Registers 19 January 1987 be written twice to cause a 10 MHz. clock to occur. This can be used to allow the microprocessor to observe and sequence the various state machines inside the SII. CLOCK (44) -- WRITE ONLY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 5.1.5.3 BHDIAG - Bus Handler Diagnostic Register This register contains various internal Bus Handler control bits. Reading it allows some additional visibility into the Bus Handler operations during test mode. BHDIAG (46) -- READ/WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |SDT|ENX|MAT|PHS|200|T25|Q9 |Q4 |DTO|TCR|DCR|ABT|SMR|RST|BM<1:0>| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o SDT - SET_DSTMO - when written to one (1), the DSSI timer is preset to a value of all one's. This enables the programmer to verify its functionality by a single clock. o ENX - SC_ENAXFER - when one (1), the SCSI_IO block is enabled, thus allowing it to transfer data. Read only. o MAT - MATCH - when one (1), the phase currently on the SCSI bus matches the internal phase expected by the SII. Read only. o PHS - PHS_CHG - when one (1), this indicates that the phase on the SCSI bus has changed. Read only. o 200 - T200US - the clock for the DSSI timeout counter. o T25 - T25US - the pulse used to time RSTOUT assertion on the bus. This is one of the taps in the DSSI timer. o Q9 - Q<9> - the tenth bit of the DSSI ripple counter. o Q4 - Q<4> - the fifth bit of the DSSI ripple counter. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 37 SCSI-II Internal Registers 19 January 1987 o DTO - DSTMO - the assertion of this signal indicates that the SII has timed out the current bus transaction. o TCR - TMRCLR - this is the clear to the generic counter used to time various activities during the selection process. o DCR - DSTCLR - this is the clear for the DSSI timer. o ABT - ABORT - this is a state in the RST control state machine. o SMR - SMRST - this is the reset for the bus control state machine. o RST - RSTOUT - this is the SCSI RSTOUT. o BM<1:0> - BUSMONITOR state bits 5.1.5.4 SIDIAG - SCSI IO Diagnostic Register This register contains various internal control bits. Reading it allows some visibility into the SCSI IO operations. SIDIAG (48) -- READ ONLY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |DIR|DPH|ISS|TAK|ODR|SNT|REQ|IDR|MAT|WON|IDL|ERR|OF<1:0>|FI<1:0>| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o DIR - SC_DIR - when one (1), data is destined for the SII. Read only. o DPH - SC_DATAPHASE - when one (1), the current bus phase is either a DATA IN or DATA OUT phase. This is used to determine if the transfer is to be done synchronously. Read only. o ISS - SD_ISSUEREQ - this signal is asserted when the data mover wants a REQ to be issued. o TAK - SD_DATATAKEN - this signal indicates that the data mover has taken a byte of incoming data from the FIFO. o ODR - SD_OUTDATARDY - this signal indicates that the data mover has data ready to send out. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 38 SCSI-II Internal Registers 19 January 1987 o SNT - SD_DATASENT - this signal indicates that the SCSI_IO has sent a byte across the SCSI bus. o REQ - SD_DATAREQ - this signal indicates that the target has requested a byte of data to be sent. o IDR - SD_INDATARDY - this signal indicates that there is at least one byte of data in the FIFO. o MAT - SC_MATCH - the assertion of this signal indicates that the pattern on the SCSI bus constitutes a valid selection of this device. o WON - SC_WON - the assertion of this signal indicates that the pattern on the SCSI bus shows that the SII has won arbitration. o IDL - SD_IDLE - this signal indicates the SCSI_IO block is idle. o ERR - SC_ERR - this signal indicates that the SCSI_IO block has detected a protocol error on the SCSI bus. o OF<1:0> - OFFSET <1:0> - the current req/ack offset. o FI<1:0> - FIFO<1:0> - the number of bytes in the FIFO. 5.1.5.5 DMDIAG - Data Mover Diagnostic Register This register contains various internal data mover control bits. This register allows further observability and controllability of the SII chip. DMDIAG (50) -- READ ONLY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |CLR|LD6|LTC|CHI|CLO|ENH|RDY| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o CLR - DP_CLR - one of the state bits of the CTRL_SM. It resets the data path. o LD6 - LOAD6 - one of the state bits of the CTRL_SM. It is used to select the value 6 for input into the LOTC register. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 39 SCSI-II Internal Registers 19 January 1987 o LTC - LOTC_LD - one of the state bits of the CTRL_SM. It is used to load the LOTC register. o CHI - CLKHI - one of the state bits of the DM_DATACTRL. It clocks the high byte of the word builder. o CLO - CLKLO - one of the state bits of the DM_DATACTRL. It clocks the low byte of the word builder. o ENH - ENHIBYTE - one of the state bits of the DM_DATACTRL. It selects the high byte for output. o RDY - READY - one of the state bits of the DM_DATACTRL. It is used to generate various handshaking signals. 5.1.5.6 MCDIAG - Main Control Diagnostic Register This register contains various internal main control bits. This register allows further observability and controllability of the SII chip. MCDIAG (52) -- READ ONLY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | LISTSM<3:0> | MAIN<2:0> | 0 |XF<1:0>| LCTRL<3:0> | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bits in this register are defined as follows: o LISTSM<3:0> - LISTSM state bits. o MAIN<2:0> - MAIN_SM state bits. o XF<1:0> - XFER_SM state bits. o LCTRL<3:0> - LISTCTRL_SM state bits. A value of 100H indicates that the SII is idle. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 40 SCSI-II Internal Registers 19 January 1987 5.2 Register Initialization Values The following table is a summary of the values which should appear in the SII registers following a hard or soft reset. Those marked by "X" indicate that the bit is indeterminate after reset. NAME BIT VALUES ---- --- ------ SDB 0000 000X XXXX XXXX SC1 0000 000X XXXX XXXX SC2 0000 0000 0000 0000 CSR 0000 0000 0000 0000 ID 0000 0000 0000 0XXX SLCSR 0000 0000 0000 0000 DESTAT 0000 0000 0000 0000 DSTMO 0000 0000 0000 0000 DATA 0000 0000 0000 0000 DMCTRL 0000 0000 0000 0000 DMLOTC 0000 0000 0000 0000 DMADDRL 0000 0000 0000 0000 DMADDRH 0000 0000 0000 0000 DMABYTE 0000 0000 0000 0000 STLP 0000 0000 0000 0000 LTLP 0000 0000 0000 0000 ILP 0000 0000 0000 0000 DSCTRL 0000 0000 0000 0000 CSTAT 0000 0100 0000 0000 DSTAT 0001 0000 0000 0XXX COMM 0000 0000 0000 0000 DICTRL 0000 0000 0000 0000 SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 41 SCSI-II Internal Registers 19 January 1987 CLOCK 0000 0000 0000 0000 BHDIAG 0101 0000 0100 1001 SIDIAG 1000 0100 0010 0000 DMDIAG 0000 0000 0000 0000 MCDIAG 0000 0001 0000 0000 SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 42 Commands 19 January 1987 6 COMMANDS The following is a description of the command set for the SII chip. Included will be operation of the chip during each command along with the various results due to execution. Registers used by the chip during the execution of the command will also be mentioned. It should be noted that these commands will be used only during normal SCSI mode operation; in DSSI mode, the SII issues the commands. Also included is a summary of the interrupts which may occur following the issuance of each command. Commands will be divided into two groups, immediate and complex. All immediate commands are executed immediately, and return no status information. Complex commands are executed as soon as possible and interrupt the microprocessor when the command has been completed. In addition, most will return status information regarding the execution of the operation. 6.1 Immediate Commands 6.1.1 Chip Reset This command will stop any operation presently executing, and reset the chip. The registers will return to their default values and the chip will be left disconnected from the SCSI bus. This command may be executed in any mode ( disconnected, initiator, or target), although it is recommended that the chip is disconnected from the SCSI bus when this command is issued. Following the issuance of this command the following interrupts may occur: - None - the SII will reset its registers and IE will be disabled( as will selection and reselection attempts). This precludes interrupts from occurring. 6.1.2 Disconnect This command will cause the SII chip to immediately release all signals on the SCSI bus. As the target, this is typically used to end a transfer. As an initiator, this is used in the case of a firmware timeout during a selection. A disconnect command, in this case, will cause the SII to abort the selection in the way described by the SCSI specification. When disconnected already, this command will cause the SII to disconnect following the next time it is selected. Only the CSTAT register is affected by this command. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 43 Commands 19 January 1987 Following the issuance of this command the following interrupts may occur: - SCH - acknowledgment of the disconnect or a device has selected or reselected the SII. The state bits can be used to determine what has happened. - RST - a device has issued RST on the bus. 6.2 Complex Commands 6.2.1 Request Data This command is only valid when in the target role. During a transfer directed towards the target (programmed I/O), the data must be requested first. The expected chip state written in the COMM register must match the state of the chip for this command to be executed. Following the issuance of this command the following interrupts may occur: - IBF - the initiator has sent a byte to the target. The following status bit may be set: - IPE - the byte just received contained a parity error. - RST - a device has asserted Reset on the SCSI bus. 6.2.2 Select This command instructs the SII to arbitrate for the SCSI bus and select a SCSI device. The ID of the device to be selected must be placed in the SLCSR register. See SLCSR definition for more detail. The SII chip will interrupt the microprocessor for one of the following reasons: - SCH - a state change has occurred for one of the following reasons. 1. The selection has been accomplished. Some of the transfer status bits (DSTAT) may be set: - BER - the target violated SCSI protocol SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 44 Commands 19 January 1987 - MIS - the target has issued a REQ in a phase other than that currently in the COMM register. - IBF - the target has sent a byte to the SII. - TBE - the target has requested a byte from the SII. 2. The SII has lost the arbitration and has been selected by another device. In this case, the ATN status bit may also be asserted. 3. The SII has lost the arbitration and has been reselected by another device. In this case, the following bits may also be set: - BER - the target violated SCSI protocol - MIS - the target has issued a REQ in a phase other than that currently in the COMM register. - IBF - the target has sent a byte to the SII. - TBE - the target has requested a byte from the SII. - RST - A device has asserted RST on the bus. 6.2.3 Information Transfer Command This command allows the transfer of information to or from this SII. The direction of the transfer is contained in the bus phase, which can also be found in the COMM register. The state of the chip must match the expected state written to the COMM register. This command can be aborted by clearing bit <11> in the COMM register. This command is not cleared when the SII disconnects from the bus, or when RSTIN is asserted. The SII will interrupt the microprocessor for the following reasons: - DNE - The transfer was completed. The transfer status bits can be used to determine if completed successfully. The following transfer status bits may be set: - TCZ - The transfer counter has a zero count. In DMA mode, all bytes were received or transferred. - IPE - The SII received a byte with a parity error. In the target role, the DMLOTC register contains the number of bytes not sent (or received). In the initiator role, the SII must continue to accept data. However, the chip SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 45 Commands 19 January 1987 will automatically assert ATN on the bus. - OBB - The DMA transfer has ended on an odd byte boundary. The DSTAT will also indicate if the initiator has asserted ATN during the transfer. - IBF - The SII has received a byte while the DataMover was idle (SII was in programmed I/O mode or the DMA was completed and more data arrived.) - TBE - A byte has been requested from the SII while the DataMover was idle (SII was in programmed I/O mode or the DMA was completed and more data was requested.) - SCH - When connected as an initiator, the attached target disconnects. - MIS - When connected as an initiator, the target changes the phase and sends a REQ. - RST - Reset is asserted on the SCSI bus. - BER - A bus error occurs during the operation. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 46 SCSI Mode 19 January 1987 7 SCSI MODE While the SII is operating in SCSI mode, it behaves quite similar to most industry-standard SCSI protocol controller chips. The following is a detailed description explaining the procedure needed to execute many SCSI-type functions: 7.1 Initiator Selection Of A Target 1. Begin by loading the ID of the device to be selected into the SLCSR register. 2. Bits <11:7> of the COMM register should be set to 01000B. This will instruct the SII to attempt to select the desired device. Bit 15 should be cleared since no DMA is involved. Bit 12 should be cleared since this is not a reselection. Should this SII win arbitration, IGS will be asserted. ATN and RST will both remain deasserted. The command code for selection would be 0400H. At this time, it is advisable to begin a firmware timer. 3. At the next detection of a bus free phase, the SII will arbitrate for the SCSI bus. Several actions may result from this: - The SII loses the arbitration and, before the software timeout, is selected by another device. In this case, the SII interrupts with the SCH bit set in the CSTAT register. Since the SII is now connected to another device, the SELECT command is forgotten. - The SII wins the arbitration (before the timeout interval) and the selected device responds. In this case, the SII interrupts with the SCH bit set in the CSTAT register. - No interrupt is generated before the software timer expires. The first two situations are straight forward. The last, however, is slightly more involved. In this case, the software must evaluate which of the following situations has occurred: - The SII has won the arbitration and the selected device did not respond. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 47 SCSI Mode 19 January 1987 - The SII lost the arbitration. It continued to attempt the selection at each successive detection of a bus free phase. However, it was unsuccessful in gaining control of the SCSI bus before the software timer expired. By reading the CSTAT, the microprocessor can tell which of these conditions exists. If the SII is currently attempting selection, the SIP bit (and only this bit) in the CSTAT will be asserted. If this is true, the software may abort the selection by issuing a DISCONNECT command. The SII will abort the selection in the way explained in the SCSI specification and clear the SIP bit. If the SII hasn't been successful in gaining control of the SCSI bus, the LST bit in the CSTAT register will be asserted. In this case, the microprocessor may wish to restart the software timer. 7.2 Initiator Selection With ATN Of A Target This procedure is similar to that detailed above. Only the differences will be pointed out. 1. Begin by loading the ID on the device to be selected into the SLCSR register. 2. Bits <11:7> of the COMM register should be set to 01000B. This will instruct the SII to attempt to select the desired device. Bit 15 should be cleared since no DMA is involved. Bit 12 should be clear since this is not a reselection. Should this SII win arbitration, IGS will be asserted. ATN will be asserted by writing bit 3 to one. The command code for selection with ATN would be 0408H. 3. The rest follows the procedure explained for selection. 7.3 Target Reselection Of An Initiator This procedure is similar to that detailed for initiator selection. Only the differences will be pointed out. 1. Begin by loading the ID on the device to be reselected into the SLCSR register. 2. Write 1400H to the COMM register. This will instruct the SII, with RSL bit set, to attempt to reselect the desired device. This also causes the I/O line to be asserted once the SII gains control of the SCSI bus. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 48 SCSI Mode 19 January 1987 3. The rest follows the procedure explained for selection. 7.4 Information Transfers This will detail the steps needed to perform an information transfer in both DMA and programmed I/O mode. 7.4.1 Initiator Information Transfers Information transfers require that the expected phase and state match those which exist currently or the transfer will not take place. 7.4.1.1 DMA Operations In this mode, the SII will automatically transfer information without microprocessor intervention (excepting error conditions). 1. Typically, the SII will generate a MIS interrupt, signaling the microprocessor that a bus phase change has occurred. Reading the DSTAT register will inform the microprocessor which phase the bus has transitioned to. 2. Load the starting byte address of the buffer area into the DMADDRL and DMADDRH registers. The SII will begin to read or deposit information from this address. 3. Load the DMLOTC register with the numbers of bytes which are to be transferred during this operation. 4. If this is a write to memory and the starting address is odd, the DMABYTE register can be loaded at this time. This will insure that a particular value is written into the low byte of the first word in the transfer. 5. Write the command code to the COMM register. This will consist of bit 15 set since this operation involves DMA. along with bits <11:7> set to 10000B. The phase bits and state bits must match those in the DSTAT and CSTAT registers if the transfer is to take place. A COMMAND OUT using DMA would be encoded as 8862H by the initiator. 6. The SII will interrupt some time later for one of the following reasons: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 49 SCSI Mode 19 January 1987 - SCH - The attached target disconnects. - RST - Reset has been asserted on the SCSI bus. - BER - A bus protocol error has occurred. - DNE - the transfer was completed. - MIS - the target has changed phase. - TBE - the target requested more bytes of information than indicated by the DMLOTC. - IBF - The target changes the information phase and sends data or the target sends more data than indicated by the DMLOTC. With the last four, the following status bits may be set: - TCZ - The transfer counter has reached zero, and all bytes were transferred. - IPE - While receiving data, a parity error occurs. In this case, it must continue to receive data. However, the chip will assert ATN on the bus. The assertion of both DNE and MIS indicates that the operation was successful and the target has now begun a new operation. NOTE The DMA operation can be aborted by the microprocessor by clearing bit <11> in the COMM register. The microprocessor should then wait for a DNE interrupt before continuing. 7.4.1.2 Programmed I/O Transfers In this mode, the microprocessor must read (or write) each byte that is transferred on the SCSI bus. This is only recommended for one byte transfers. 1. Typically, the SII will generate a MIS interrupt, signaling the microprocessor that a bus phase change has occurred, along with either IBF or TBE status. 2. The microprocessor reads (or writes) the DATA register. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 50 SCSI Mode 19 January 1987 3. Write the command code to the COMM register. This will consist of bit 15 cleared since this operation does not involve DMA. along with bits <11:7> set to 10000B. The phase bits must match those in the DSTAT register if the transfer is to take place. A COMMAND OUT using programmed I/O would be encoded as 0862H by the initiator. Interrupts may also occur for the following reasons: - SCH - The attached target disconnects. - RST - Reset has been asserted on the SCSI bus. - BER - A bus protocol error has occurred. - TBE - The target requests another byte (a phase change need not occur). - IBF - The target sends another byte ( a phase change need not occur). - MIS - The target has changed phase. The following status bit may be set: - IPE - While receiving data, a parity error occurs. In this case, the chip will assert ATN on the bus. Programmed I/O is on a byte basis. In other words, a command to receive or send data in non-DMA mode is valid for only one byte. If multiple bytes are to be transferred in this mode, each new byte must be accompanied by a new command. 7.4.2 Target Information Transfers 7.4.2.1 DMA Operations In this mode, the SII will automatically transfer information without microprocessor intervention (excepting error conditions). 1. Typically, the SII will generate an interrupt, signaling that the previous command has been completed or the SII has been selected. 2. Load the starting byte address of the buffer area into the DMADDRL and DMADDRH registers. The SII will begin to read or deposit information from this address. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 51 SCSI Mode 19 January 1987 3. Load the DMLOTC register with the numbers of bytes which are to be transferred during this operation. 4. If this is a write to memory and the starting address is odd, the DMABYTE register can be loaded at this time. This will insure that a particular value is written into the low byte of the first word in the transfer. 5. Write the bus phase which this transfer will take place in the COMM register. This should be written before the command is written to allow time for it to settle on the bus. 6. Write the command code to the COMM register. This will consist of bit 15 set since this operation involves DMA, along with bits <11:7> set to 10000B. The desired phase should be encoded in bits <4:2>. For example, a target may issue a COMMAND OUT using DMA by writing 8852H to the COMM register. 7. The SII will interrupt some time later for one of the following reasons: - RST - Reset has been asserted on the SCSI bus. - BER - A bus protocol error has occurred. - DNE - the operation is done. One or more of the following status bits may also be set: - TCZ - The transfer counter has reached zero, and the transfer has been completed. - IPE - While receiving data, a parity error occurs. In this case, it will stop asserting REQ (thus stopping the transfer). DMLOTC will indicate the number of bytes not transferred. - ATN - The initiator asserts ATN. NOTE The DMA operation can be aborted by the microprocessor by clearing bit <11> in the COMM register. The microprocessor should then wait for a DNE interrupt before continuing. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 52 SCSI Mode 19 January 1987 7.4.2.2 Programmed I/O Transfers In this mode, the microprocessor must read (or write) each byte that is transferred on the SCSI bus. This is only recommended for one byte transfers. o Reads 1. Typically, the SII will interrupt with a DNE interrupt. 2. A REQDATA command must be issued. The command code for this would be 0252H to request data in COMMAND OUT phase. 3. Wait for a IBF interrupt. 4. Read the data register. 5. Write the command code to the COMM register. This would be 0852H in this case. This clears the IBF signal. The following status bits may or may not be set: - IPE - While receiving data, a parity error occurs. In this case, the chip will stop asserting REQs on the bus (thus terminating the operation). - ATN - The initiator asserts ATN on the bus. 6. A DNE interrupt will result. This signals the end of the operation. o Writes 1. Typically, the SII will interrupt with a DNE interrupt. 2. Next, write the DATA register with the value to be sent. 3. Write the command code to the COMM register. For the case of a DATA IN transfer, this code would be 0851H. 4. A DNE interrupt will result some time later. This signals the end of the operation. 7.5 Initiator Setting ATN This can be done only in the initiator role. Typically this is used to allow the initiator to request a MSG OUT phase. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 53 SCSI Mode 19 January 1987 This is accomplished by reading the COMM register, 'or'ing 0008H and writing this value back to the COMM register. This allows the previous command to continue. Note that the SII will automatically assert ATN if it detects a parity error during an initiator transfer. 7.6 SII Setting RST This can be performed at any time by writing 4000H to the COMM register. Note that in SCSI mode, this is equivalent to a hard reset of all devices. 7.7 Command Chaining Since the Request Data and Transfer Info commands are only executed when the state is matched, command chaining is possible. For example, it might be desirable to select another device with ATN and if successful, expect a Message Out phase and do a DMA. This is possible with a single command. The DataMover registers (DMLOTC, DMADDRL, DMADDRH, DMABYTE, etc.) should be loaded first. Next the SLCSR register should be loaded. Lastly, the command should be loaded. The command would include both a select and info transfer command. In addition, the expected state of connected, not destination and initiator must be loaded. The select command executes immediately. If the SII is successful in selecting the remote device, the chip's state will match the expected state and the DMA will occur. However, if the chip is selected or the phase does not match the expected phase, no data transfer will take place. There are several other variations of this, which are enumerated below. o Wait for Select, then DMA The command that must be loaded is: 1000100001010xxx This indicates: DMA enabled Transfer Info command Expected state: connected as target, destination Phase: whatever desired o Wait for Select, then Request Data The command that must be loaded is: 0000001001010xxx SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 54 SCSI Mode 19 January 1987 This indicates: Request Data command Expected state: connected as target, destination Phase: whatever desired o Wait for Select with ATN, then DMA The command that must be loaded is: 1000100001011xxx This indicates: DMA enabled Transfer Info command Expected state: connected as target, destination and ATN set during selection Phase: whatever desired o Wait for Select with ATN, then Request Data The command that must be loaded is: 0000001001011xxx This indicates: Request Data command Expected state: connected as target, destination and ATN set during selection Phase: whatever desired o Select, then DMA The command that must be loaded is: 1000110001100xxx This indicates: DMA enabled Transfer Info command Select command Expected state: connected as initiator, origin Phase: must match desired phase o Select with ATN, then DMA The command that must be loaded is: 1000110001101xxx This indicates: DMA enabled Transfer Info command Select command Expected state: connected as initiator, origin SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 55 SCSI Mode 19 January 1987 ATN set during selection Phase: must match desired phase o Reselect, then DMA The command that must be loaded is: 1001110001110xxx This indicates: DMA enabled Transfer Info command Select command, RSL set (reselect) Expected state: connected as target, origin Phase: whatever desired o Reselect, then Request Data The command that must be loaded is: 1001011001110xxx This indicates: Request Data command Select command, RSL set (reselect) Expected state: connected as target, origin Phase: whatever desired o Wait for reselect, then DMA The command that must be loaded is: 1000100001000xxx This indicates: DMA enabled Transfer Info command Expected state: connected as initiator, destination Phase: must match desired phase All commands using DMA can also be done in programmed I/O mode by clearing the DMA bit. NOTE These are the only commands that can be chained! SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 56 DSSI Mode 19 January 1987 8 DSSI MODE This mode of the SII was intended specifically to be used with Digital's Small Storage Interconnect. The SII provides many of the bus window functions required by the data link layer (refer to the DSSI Data Link Layer specification). It does so using a minimal number of microprocessor interrupts. 8.1 DSSI Bus Sequences The following is taken from the aforementioned specification. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 57 DSSI Mode 19 January 1987 +---------------+ | | | Bus Free |<------+ | | | +---------------+ | | | V | +---------------+ | | | (1) | | Arbitration |-------+ | | | +---------------+ | | | V | +---------------+ | | | (2) | | Selection |-------+ | | | +---------------+ | | | V | +---------------+ | (4) | | (3) | +-------| Command Out |-------+ | | | | | +---------------+ | | | | | V | | +---------------+ | | | | (5) | | | Data Out |-------+ | | | | | +---------------+ | | | | | V | | +---------------+ | | | | | +------>| Status In |-------+ | | +---------------+ The normal path follows vertically downward. Exception paths are listed below: 1. The initiator arbitrates and loses. 2. The target failed to respond or responded with an unexpected bus phase. 3. The operation was timed out or the target responded with unexpected phase. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 58 DSSI Mode 19 January 1987 4. The target detected a parity error or information mismatch in the command, or the target did not have any buffer space available. 5. The operation was timed out or the target responded with an unexpected phase. 8.2 Command Block Data Structure When operating in DSSI mode, the SII expects certain data structures to be established in memory. These will be known as command blocks. The following is a pictorial description of this block. Note that these structures must lie on quad-word boundaries (i.e. the least significant three address bits must be zero). COMMAND BLOCK +-----------------------------------------------+ base+0 | Thread word | +-----------------------------------------------+ base+2 | Status word | +-----------------------------------------------+ base+4 | Command word | +-----------------------------------------------+ base+6 | Command Bytes (6) | +-----------------------------------------------+ These elements are defined as follows: o Thread word - pointer to next such structure in memory. A zero (0) in this location indicates this is the end of the linked list. The address will be a quadword address. In other words, the address will be the byte address, shifted to the right by two places. o Status word - this word indicates the status of the transfer. This word is necessary so that the microprocessor can know which buffers have been completed by the SII. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |DNE| - | - | - | - | - | - | - |RST|TMO|XSM|BPH|STT|PHS|DSA|PAR| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 59 DSSI Mode 19 January 1987 The bit fields in this memory word represent the following: o DNE - Bit 15 will be set (1) if the SII has used this block (regardless of result). If this bit is set when the SII begins processing this element, the block is skipped and the operation continues. (Inbound and Outbound Buffers) o RST - Reset - Set to one if RST was asserted on the bus during this transfer. (Inbound and Outbound Buffers) NOTE If RST was asserted before the SII reached status phase, the SII will clear OUTEN in the DSCTRL register and interrupt without writing any status. o TMO - Timeout - Set to one if DSTMO was asserted during this transfer. (Inbound and Outbound Buffers) NOTE If DSTMO was asserted before the SII reached status phase, the SII will clear OUTEN in the DSCTRL register and interrupt without writing any status. o XSM - Checksum - Set to one if the received checksum does not agree with that computed by the SII. Inbound Buffers Only. o BPH - Bad Phase - Set to one if an illegal DSSI phase was entered by the target. Outbound Buffers Only. o STT - Status - Set to one if ACK was not returned by the target. Outbound Buffers Only. o PHS - Phase - Set to one if the phase changed before the initiator expected. Outbound Buffers Only. o DSA - DSSI - Set to one if the target detected an error in the command bytes. Inbound Buffers Only. o PAR - Parity - Set to one if a parity error was detected. Inbound and Outbound Buffers. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 60 DSSI Mode 19 January 1987 Please note that the following cases will not cause status to be written in memory: 1. RST asserted before status phase was reached. 2. Initiator selects non-existent device (timeout will cause RST). 3. Target disconnects before status phase was reached. 4. Target selected with Attention 5. Initiator attempts to select a non-DSSI device. o Command word - this word contains information regarding the transfer. This word looks as follows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |IE | - | - | - | - | - | - | - | - | - | - | - | - | DEST ID | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The bit fields in this memory word represent the following: o IE - when asserted (1), the SII will interrupt the local intelligence upon the completion (successful or not) of this packet. When cleared (0), the SII will not interrupt. o DEST ID - the ID of the target to be selected (only used for outbound work). o Command - the 6 byte sequence, sent in COMMAND OUT phase by the initiator is stored here. Contained in these bytes is the number of data bytes which will be transferred by the initiator in the DATA OUT phase. 8.3 Structures For Data The remaining part of the SII data structures varies depending on the direction of the transfer. For "inbound" work, the data area follows immediately after the Command Block described above. For "outbound" work, the structure is different. Following the Command Block is the length in bytes of the next segment. Next is its address (shifted right twice). Pictorially, this SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 61 DSSI Mode 19 January 1987 link appears as follows: +---+-------------------------------------------+ |LNK| LENGTH OF NEXT SEGMENT | +---+-------------------------------------------+ | ADDRESS OF NEXT SEGMENT (ADDRESS BITS<17:02> | +-----------------------------------------------+ The LNK flag indicates if there is a segment following the next one. This bit is clear if the next segment is the last in this transfer. Each segment of data (except the final one) must have the above described link at the end of it. The number of linked segments is unlimited. 8.4 Linked List Operation The SII uses three lists, one for short inbound "work" ,one for long inbound "work" and one for outbound "work". The following diagram serves to illustrate this. Free Free Buffer Buffer STLP #1 #2 +-------+ +-------+ +-------+ | o---+------>| o---+------>| o---+---> etc. +-------+ +-------+ +-------+ |status | |status | | area | | area | +-------+ +-------+ |command| |command| | word | | word | +-------+ +-------+ |command| |command| | area | | area | +-------+ +-------+ | data | | data | | area | | area | +-------+ +-------+ For inbound short data, the SII uses the STLP register to determine the address of the next free short buffer. As the SII fills a free buffer, it will reload the TLP with the thread word of the just filled buffer. This process continues until the SII reads a thread word of zero (0). This indicates that there are no free short buffers available to the SII. The TZ bit in the CSTAT register will be set. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 62 DSSI Mode 19 January 1987 Free Free Buffer Buffer LTLP #1 #2 +-------+ +-------+ +-------+ | o---+------>| o---+------>| o---+---> etc. +-------+ +-------+ +-------+ |status | |status | | area | | area | +-------+ +-------+ |command| |command| | word | | word | +-------+ +-------+ |command| |command| | area | | area | +-------+ +-------+ . . . . . . . . . . . . | data | | data | | area | | area | . . . . . . . . . . . . +-------+ +-------+ For inbound long data, the SII uses the LTLP register to determine the address of the next free long buffer. As the SII fills a free buffer, it will reload the TLP with the thread word of the just filled buffer. This process continues until the SII reads a thread word of zero (0). This indicates that there are no free long buffers available to the SII. The TZ bit in the CSTAT register will be set. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 63 DSSI Mode 19 January 1987 Ready Ready Buffer Buffer ILP #1 #2 +-------+ +-------+ +-------+ | o---+------>| o---+------>| o---+---> etc. +-------+ +-------+ +-------+ |status | |status | | area | | area | +-------+ +-------+ |command| |command| | word | | word | +-------+ +-------+ |command| |command| | bytes | | bytes | +-------+ +-------+ |1|LOTC | |0| LOTC| +-------+ +-------+ +-----------o | | o-----------+ | +-------+ +-------+ | | | | | +------>+-------+ +-------+<------+ | data | | data | | bytes | | bytes | +-------+ +--->+-------+ |0|LOTC | | | data | +-------+ | | bytes | | o------+ +-------+ +-------+ For outbound data, the SII uses the ILP register to determine the address of the next "work" buffer. As the SII processes an outbound buffer, it will reload the DMADDR with the link word of the next segment as long as the LNK is enabled. This chaining continues until of LNK value of zero (0) is encountered. The SII will transfer the next segment, then deposit the status of the entire transfer in the status area of the command block. This process continues until the SII reads a thread word of zero (0). This indicates that there are no outbound buffers left to process. The SII clears its OUTEN bit in the DSCTRL register and stops all outbound work. If an error of any kind occurs during the processing of an outbound buffer, the SII will stop work on the outbound list by clearing the OUT_EN bit in the DSCTRL register. 8.5 Operation During DSSI Transfer The following is a detailed description of the operation of the SII during a DSSI operation. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 64 DSSI Mode 19 January 1987 8.5.1 Target Operations The following is a detailed description of the SII functions as a target during a typical DSSI atomic transfer. 1. The SII is selected by an initiator. 2. It responds to the selection by asserting BSY and enters COMMAND OUT phase. 3. The SII checks that the selecting device is indeed a DSSI device by checking its status bit in the DSCTRL register. If it is not a DSSI device, an interrupt (the SCH bit in the CSTAT register will be set) is generated. 4. Assuming this is a DSSI device, the SII continues by enabling its Target Timeout counter (value is contained in DSTMO register). Should this timer expire, the SII will immediately disconnect from the bus. 5. The SII requests and waits for the first byte to determine if this is a long or short transfer. 6. Knowing that this is a DSSI mode transfer, the SII checks the contents of the appropriate Target List Pointer (TLP). Should this value be zero (0), the SII continues with step 21. 7. The SII begins reading memory from the address specified by the appropriate TLP register. The first word (thread) contains the address of the next list element and is stored in the DMADDR register. 8. The next word (status) is read. If bit 15 (Done) is set, the value stored in the DMADDR register is loaded into the TLP and the SII continues with step 6. 9. The SII reads the next word (command) to see if an interrupt should be generated following the completion of this element. 10. The SII also loads six (6) into the DMLOTC. 11. The SII pulls the data from the initiator and stores it in RAM, beginning at the value specified in the TLP register, offset by six. Should an error in transmission occurred anytime in this sequence, the SII will stop generating REQs (thereby ending the transfer). The SII will continue with step 21. 12. The command byte is checked for validity. If it is not the required value, continue with step 21. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 65 DSSI Mode 19 January 1987 13. The REQ/ACK offset from the second command byte is loaded into the DMCTRL register. 14. The SII will check the destination address in the command packet. If there is non-agreement with the number in the ID register, it will continue with step 21. 15. The SII will check the source address in the command packet. If not the same as the DESTAT register, it will continue with step 21. 16. When the command is done (seven bytes have been delivered and six deposited into memory), it compares the incoming checksum (the seventh byte received) with that which it has calculated for the six command bytes. If there is a discrepancy, the SII continues with step 21. 17. If the checksum is valid, the SII loads the DMLOTC with the number of data bytes to be transferred. This value is still present in the SII "outbound word latch" since the length information was contained in the last two bytes which were deposited into memory. 18. It enters DATA OUT phase and pulls data from the initiator until DMLOTC is zero(0). This is done using synchronous transfer mode. Should an error in transmission occurred anytime in this sequence, the SII will stop generating REQs (thereby ending the transfer). The SII continues with step 21. 19. Following receipt of all information bytes, the SII compares the incoming checksum with that which it has generated. If these do not agree, the SII continues with step 21. 20. It enters STATUS IN phase and passes ACK to the initiator. The SII continues with step 22. 21. The SII enters the STATUS IN phase and passes NACK to the initiator. 22. The SII loads the DMADDR register from the address specified by the TLP. 23. The SII loads an internal status code into the address specified in the TLP register, offset by two. 24. The SII loads the TLP register with the value saved in step 22. 25. The SII disconnects from the DSSI bus. 26. If interrupts are enabled for this buffer (LDN bit will be set), the SII will interrupt the microprocessor to inform it that servicing is required. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 66 DSSI Mode 19 January 1987 8.5.2 Initiator Operations The following is a detailed description of the SII functions as an initiator during a typical DSSI atomic transfer. 1. The ILP is written and the OUTEN bit in the DSCTRL register is set by the microprocessor. 2. During the next bus free period, the SII will arbitrate for the bus if the ILP is not zero. It will also start the initiator timer. Should this timer expire, the SII will assert RST on the DSSI bus and continue with step 18. 3. If the SII gains control of the bus, it will begin reading memory from the location specified by the ILP. The first word (thread) read is the address of the next list element and is stored in the DMADDR register. 4. The next word (status) is read. If bit 15 is set, the SII will load the ILP with the value saved in the previous step into the ILP and continue with step 3. 5. The SII reads the next word (command), and loads the SLCSR with its contents. 6. If the DSCTRL bit corresponding to this node is not set, the SII will interrupt now (BUF bit will be set) and will not execute the rest of the DSSI sequence. 7. The SII selects a target. 8. Knowing that this is a DSSI mode transfer, the SII expects COMMAND OUT phase. A STATUS IN phase causes a jump to step 16. Any other phase results in the SII asserting RST on the DSSI bus and continuing with step 18. 9. The SII loads six (6) into the DMLOTC. 10. Since the SII overhead and the command bytes to be sent to the target are contiguous with the element header information, a new value does not have to be loaded into the DMADDR register. The SII simply continues the current DMA operation. 11. The SII sends data to the target, getting the data from memory starting at the address specified in the DMADDR register, offset by six. While sending the data, the SII generates a checksum. This checksum is simply the XOR of all command bytes. Following the sixth byte, this checksum is sent. 12. Following the transmission of the seventh byte, the SII expects the target to go to DATA OUT phase. A STATUS IN phase causes a jump to step 16. Any other phase causes the SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 67 DSSI Mode 19 January 1987 SII to assert RST on the DSSI bus and continue with step 18. 13. The SII loads the number of data bytes to be sent in the next segment into the DMLOTC. This value is the next word in memory. 14. The SII gets the address of the next segment by reading the next word in memory. It stores this in the DMADDR register. 15. The SII does a new address cycle using this segment pointer. It then sends data to the target until DMLOTC is zero(0). This is done using synchronous transfer mode. If at any time during this transfer, the bus phase changes to STATUS IN, the SII will jump to step 16. If LNK is enabled, the SII goes back to step 13. Otherwise, it will send a checksum for the data bytes after sending all the information. 16. The SII expects STATUS IN phase and receives one byte of status from target. Any other phase causes the SII to set RST on the DSSI and continue with step 18. 17. The SII re-reads the next pointer and stores it in the DMADDR register. 18. The SII loads some internal status, into the address specified in the ILP register, offset by two. 19. The remote device should disconnect now. No other bus phases are expected. 20. If the previous transfer was completed successfully (i.e. an "ACK" was received), the SII will continue with the next step. If not, the SII will stop execution in the initiator role ONLY by clearing OUTEN in the DSCTRL register. 21. The SII loads ILP register with the value saved in step 17. 22. Should the value of the ILP register be non-zero, it repeats this sequence. If IE has been asserted in the initiator word, it will interrupt at this point (LDN will be set). 8.6 Adding To A Linked List The following enumerates the steps required to dynamically add new buffers to the TLP and ILP lists. 1. Fill in the new buffer command block and insure that the MSB of the status word is zero. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 68 DSSI Mode 19 January 1987 2. The thread word of the new buffer must be zero. 3. Write the last item on either the ILP or TLP list with the new thread word, pointing to the new buffer. 4. If the ILP (TLP) is zero, write it with the address of the new buffer. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 69 Internal Sub-blocks 19 January 1987 9 INTERNAL SUB-BLOCKS The SII can be divided into five major blocks. Each of these blocks performs a specific function with minimal interfacing to other blocks. These blocks will be described in detail below. 9.1 Bus Handler This block handles the generation of all SCSI bus control signals, as well as the SCSI "real-time" functions (i.e. selection/selection detection processes). The Bus Handler is further divided into smaller sub-blocks, each of which perform a specific function. One such sub-block consists of a state machine, which implements the SCSI selection/reselection protocol. When a SELECT command is issued, this machine waits for a bus free phase. It then follows the SCSI protocol to arbitrate for the bus. If successful, it continues the process by attempting to select the desired node. If this node responds, it generates a "SelDone" interrupt. If it failed to gain control of the SCSI bus and was, in fact, selected itself, it follows the necessary steps to acknowledge the selection. The state machine will continue to arbitrate at every bus free phase until either it is successful or it is selected by another device. This state machine is used in both DSSI and SCSI modes. This state machine also implements the DSSI specific transfer timing functionality. If enabled, all bus transfers are timed and appropriate action is taken should these transfer consume too much time. Another sub-block of the Bus Handler contains the actual DSSI timer. This timer is controlled by the state machine described above and produces an output signal when it expires. Several sub-blocks are concerned with the receipt and generation of the bi-directional control signals. These signals are grouped according to functionality and fall into three categories: 1. Bus - those signals used to gain control of the bus 2. RD - those signals used to control the external receiver/driver chip 3. Control - those signals used to control an information transfer All IO cells in this block contain several multiplexers to allow the microprocessor to appear to act as the SCSI bus to the SII. This is especially useful during diagnostic tests. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 70 Internal Sub-blocks 19 January 1987 This block controls the activities of the SCSI Input/Output block through various control lines and receives status from this block. This block is in turn controlled by the Main Control block and returns certain status information to it. 9.2 SCSI Input/Output This block is the SCSI input and output data path of the SII chip. It also monitors the data bus, reporting status to the Bus Handler block. The SCSI Input/Output section contains several sub-blocks. One of these sub-blocks is the FIFO. There is a three byte FIFO, used to receive information during synchronous data transfers. The mode of the FIFO is controlled by the Bus Handler block. The second block is the actual data input/output path. It is here that the different sources of output data are multiplexed. In addition to the data transferred during information transfers, this block generates the data patterns needed during arbitration and selection. This block also informs the Bus Handler when the data pattern on the bus matches that used during a selection process. Lastly, all the IO cells contain several multiplexers to allow the microprocessor to act as the SCSI bus to the SII chip. The last sub-block in the SCSI Input/Output block handles the generation of SCSI Requests and Acknowledges. Based on the transfer mode, it monitors the incoming control signal and generates its own. This sub-block also communicates with the Data Mover to allow passage of data between the two blocks and also keeps track of the FIFO status and the ReqAck offset. 9.3 Data Mover The Data Mover is responsible for the passage of data from the SCSI Input/ Output block to the II bus interface. It also performs certain DSSI specific functions under the direction of the Main Control block. The outbound data path consists of a buffer, used to disassemble words. The desired byte is then sent onto the SCSI Input/Output block to be transmitted. The sub-block also generates and transfers the checksum of all bytes which it transfers, again under the instruction of the Main Control. The inbound data path consists of a buffer, used to assemble bytes into words. This sub-block also provides DSSI specific functions, such as: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 71 Internal Sub-blocks 19 January 1987 1. Compare command byte to DSSI opcode 2. Check Destination ID 3. Check Source ID 4. Move ReqAck Offset into DMCTRL register 5. Validating checksum 6. Checking incoming status The status signals generated by this block are used by the control sub-block. The control sub-block contains a DMA engine, which uses a handshaking protocol to communicate with both the SCSI Input/Output block and the II block. It also contains a state machine, used only in DSSI mode. This state machine checks the various status bits generated by the inbound data path and reports any errors to the Main Control block. The control sub-block also generates other status information pertaining to the data transfer readable in the INSTAT register. 9.4 II Block The II Block is the SII interface to the backport memory. This block is responsible for the II bus protocol, data flow, bus arbitration and register accesses. These functions make up the four major sub-blocks of the II Block. The II bus protocol block generates the required address and data strobes, and the write signal appropriately. It uses the incoming ready signal to terminate all data transfers. This sub-block also handles the II bus arbitration. Before attempting any data transfer, it examines the chip select signal to determine if the microprocessor wishes to read or write a register. This function is given priority over data transfers. A separate block controls the register access timing. Upon detection of the microprocessor's desire to perform a register access, a state machine is started. This state machine generates the appropriate address and data enable signals. If the operation is a read, this sub-block enables the data from the selected register onto the outbound bus. Should the operation be a write, the data is latched into a holding register. The state machine then continues by generating a write strobe to the correct register bank. Last is the actual data path. There are four internal sources of outbound data: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 72 Internal Sub-blocks 19 January 1987 1. Register Data 2. Linked List Data 3. Data Mover Data 4. Address Based on various control signals, the proper data is driven onto the data bus. In addition, there are three destinations for inbound data: 1. Register Address 2. Register Data 3. Memory Data Incoming data is loaded into the proper input latches based on control signals supplied by the other sub-blocks. With the exception of register information, this block only communicates with the Main Control and Data Mover blocks. 9.5 Main Control The Main Control block is the central control block of the SII chip. While operating in SCSI mode, all command and status information visible to the microprocessor is contained in this block. All actions performed by the Bus Handler (selection/reselection), and the Data Mover (DMA/information transfers) are initiated by this block. While operating in DSSI mode, this block uses a set of state machines to initiate the above mentioned functions without microprocessor intervention. All errors are still reported to the microprocessor; however, error-free transmissions can occur autonomously. The SII gets buffer addresses from memory using a linked list machine. This constitutes the second major sub-block of the Main Control block. The linked list machine performs several functions: 1. Checks that the current buffer is unused 2. Loads the command word into the appropriate register 3. Writes status information into memory regarding the just completed transfer 4. Finds the address of the next buffer These functions are provided by state machines residing in this SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 73 Internal Sub-blocks 19 January 1987 block. These state machines are started by the main control state machine. This block reports certain status information back to the main control state machine. This includes: 1. No more inbound buffers 2. No more outbound work to do 3. Non-DSSI buffer 4. Interrupt following completion of current buffer This sub-block also provides the interface to the II block, even in SCSI mode. All information related to memory addressing is contained in this block. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 74 Back Port Modes 19 January 1987 10 BACK PORT MODES This section offers an introduction to the two backport modes implemented in the SII. The differences between them are noted below. 10.1 Back Port Mode 1 - (Phoenix Mode) 10.1.1 Introduction This was the original backport that the SII was to have. This mode interfaces directly to Phoenix, but can be adapted for other applications. This backport mode is particularly useful for devices with several high bandwidth ports. This mode gives the designer a great deal of flexibility due to the following: 1. In this mode, the SII waits for the assertion of RDY before terminating a cycle. This allows the SII to be held off from memory. The designer can therefore design an external memory arbiter. 2. The SII is capable of addressing 256 kB of memory. 3. Most transfers are sequential in nature. For these transfers, the SII simply asserts data strobe. Discontinuities in memory accesses require a new address strobe. This allows a FIFO to be easily added. 10.2 Back Port Mode 2 - (Arbitrating Mode) 10.2.1 Introduction A second backport mode was added for the TF family of products. This mode incorporates some additional functionality, such as an arbitrated bus, while making some assumptions about the external hardware. These assumptions include: 1. Other hardware residing on the SII bus is not "bursty" (ie. single accesses). 2. Other hardware rarely accesses the memory bus (low throughput). 3. Memory access times are faster than 150 ns. 4. An external counter having a "LOAD" and "CLK" input is used. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 75 Back Port Modes 19 January 1987 5. There is no more than 128kB of memory. This set of assumptions fits nicely with the architecture of a tape drive. This mode, however, is not meant for devices with two or more high throughput ports, such as a disk drive or adapter. 10.2.2 Additional Functionality 10.2.2.1 Memory Arbitration The SII will handle the arbitration of the memory bus. Other hardware will request this bus from the SII by asserting HP_RDY(HP_BUSREQ). After the current cycle (or immediately if the SII is idle), the SII will relinquish the bus by tristating its data bus and signal this by asserting HP_BUSGRANT. The SII will continue to assert HP_BUSGRANT until the requesting device has deasserted HP_RDY. These requests must be short in duration and infrequent if SII throughput is not to be degraded. While the SII is bus master, it assumes it controls the memory and will never be held off. Therefore, all data cycle will be of fixed 150 ns. duration. 10.2.2.2 Address Counter Control The SII will generate the control signals needed to use an external counter with no "glue" chips. In this mode, HP_ADDR16 becomes the HP_LOAD signal (see following section on addressing). As such, it is asserted while the address is on the SII DAL lines. HP_AS becomes the counter clock(HP_CTRCLK). It is asserted in the center of the LOAD signal (100 ns. after the assertion of LOAD) in order to load the counter. It is also asserted 100 ns. after the trailing edge of HP_DS to increment the counter. 10.2.2.3 Reduced Address Capability In order to provide the above mentioned functionality, the SII uses an address line (HP_ADDR16). The effect of this is a 50% reduction in the amount of memory the SII is able to address. The highest order address bit (address bit 17) is no longer sent from the chip. In its place on HP_DAL<0> is address bit 16. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 76 Test Strategy 19 January 1987 11 TEST STRATEGY The SII has be designed with testability in mind. Towards that end, there are several different test modes implemented in the SII. While in diagnostic mode, the microprocessor will be able to test a large percentage of the internal circuitry, as well as various interconnects on the module. This will allow a large degree of in-circuit testing without need for special hardware. 11.1 Loop Back Testing In diagnostic loop back mode, the microprocessor is able to directly control the SCSI inputs to the SII. It is also able to read the outputs which the chip generates. This will be accomplished by diverting I/O activity away from the SCSI port to the microprocessor diagnostic registers. By setting the proper bits in the CSR register (the DIA and LPB bits), the inputs to the SII internal circuitry can be switched from the actual signal pins to the diagnostic registers. This will allow the microprocessor to effectively transfer packets into buffer memory. The microprocessor can then check the buffer area to insure that the data was indeed passed correctly. Secondly, the microprocessor may set up packets in buffer memory to be "sent". Again, the data will pass through the SII and appear in the diagnostic registers, allowing the microprocessor to view and verify it. This functionality will work in both SCSI and DSSI mode. Through this test, approximately seventy to eighty percent of the gates can be exercised and tested. (see Appendix B) 11.2 Looped Connector Testing A second test procedure includes using a loop-back connector at the SCSI port. This will allow the microprocessor to verify the functionality of the SCSI port outputs, the receiver/driver chip(s), and the connections between the two. Using this connector, along with registers SDB, SC1, and SC2, it is possible to verify that the SII is able to communicate on the external bus. (see Appendix B) 11.3 Observation The SII allows the user, through the microprocessor to view many of the storage elements inside the SII. Additional diagnostic registers have been added to allow access to SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 77 Test Strategy 19 January 1987 previously hidden nodes. In addition, the SII supports a test mode, in which the system clock may be replaced. Instead, the microprocessor can generate the chip's clock by writing to the CLK register. This allows the programmer to see state machines transition so that both functionality and timing may be checked. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 78 External Operations and Timing 19 January 1987 12 EXTERNAL OPERATIONS AND TIMING This section discusses the external interfaces of the SII, especially to the memory port. Diagrams are added for clarity. 12.1 Microprocessor Read Cycles When the microprocessor wishes to read the contents of an SII register, it asserts HP_CS. Upon detection of this signal, the SII will finish any memory transaction currently in progress and service the microprocessor. The time that can elapse during this period is variable; it depends greatly on the memory bus activity. In the best case (the memory port is idle), the assertion of HP_ADREN could be as soon as 100 ns. following the assertion of HP_CS. In the worst case (the SII has just begun a new memory cycle), the microprocessor is forced to sit idle as the SII asserts HP_ AS, followed by HP_DS to the memory. The duration of this action is a function of memory bandwidth and traffic and will not be estimated here. Before the assertion of HP_ADREN, the SII will release the HP_WRITE signal, preparing for the microprocessor access. Upon the assertion of HP_ADREN, the external logic must begin to drive the register address onto the HP_DAL lines and also drive HP_WRITE. At this time, the external logic may deassert HP_CS. One HP_CLK cycle following the assertion of HP_ADREN, the SII will assert HP_AS. This does not require any reaction by the external logic. Note that this does not happen in the arbitrating mode. Two clocks later, the SII will deassert HP_ADREN, thereby ending the address portion of the cycle. The SII will latch the contents of the HP_DAL lines internally, along with the HP_WRITE signal. The external hardware may release HP_WRITE now. The SII requires no hold time on either address or HP_WRITE. Three clock cycles later, the SII will assert the HP_DATAEN signal. The SII will also drive the contents of the selected register onto the HP_DAL lines. One clock cycle later, the SII will deassert HP_AS. This signals the external logic to release HP_WRITE if it hasn't already done so. Two clock cycles later, the SII will deassert the HP_DATAEN signal, thereby ending the cycle. Data, however, will remain on the HP_DAL lines for an additional clock cycle or until the deassertion of HP_CS, whichever is later. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 79 External Operations and Timing 19 January 1987 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HP_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ (input) | | | | | |T1 | | | | | _________|___________|___________|_ HP_WRITE L----|-/ | \--------|-----------|-\----------------- | | ||T2 | | ___ | _|_|_________|___________|___________________ HP_CS L |\__|_________/_|_|_________|___________|_______________/ (input) | | | | | | | | | |T4 | |T5 | | | T3 | | | | | | | | | _________ __________|___________|__________________ HP_ADREN L |\_________/| | | (output) | | | | | | T6 | | |T8 | | | | | | |T9 | | T7 | | | _________________________________ __________________ HP_DATAEN L | | |\_________/| (output) | | | | |T10| | | T11 | ______________ | | ________|_________________ HP_AS L |\__________________|__/| | (output) | | | | | | | |T13| | | T12 | |T14| | | | | | T15 | | _________ | _________ | | ____________ HP_DAL H _________< ADDRESS >_________< DATA OUT >____________ (BiD) Times are as follows: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 80 External Operations and Timing 19 January 1987 +-------+---------------------------------------+---------------+ | Name | Description | Time | +-------+---------------------------------------+---------------+ | T1 | HP_CLK cycle time | T (50 ns. min)| +-------+-------------------------------------------------------+ | T2 | HP_WRITE hold time following HP_ADREN | 0 | | | deassertion | | +-------+---------------------------------------+---------------+ | T3 | HP_CS assertion to HP_ADREN assertion| no max | +-------+-------------------------------------------------------+ | T4 | HP_CLK rising to HP_ADREN assertion | 41 ns max | +-------+-------------------------------------------------------+ | T5 | HP_CLK rising to HP_ADREN deassertion | 38 ns max | +-------+---------------------------------------+---------------+ | T6 | HP_ADREN assertion width | 3T-10 min | +-------+---------------------------------------+---------------+ | T7 | HP_ADREN deassertion to HP_DATAEN | 3T-5 min | | | assertion | | +-------+---------------------------------------+---------------+ | T8 | HP_CLK rising to HP_DATAEN assertion | 41 ns min | +-------+---------------------------------------+---------------+ | T9 |HP_CLK rising to HP_DATAEN deassertion | 38 ns min | +-------+---------------------------------------+---------------+ | T10 | HP_ADREN assertion to HP_AS assertion | T min | +-------+---------------------------------------+---------------+ | T11 | HP_DATAEN assertion width | 3T-10 min | +-------+---------------------------------------+---------------+ | T12 | HP_AS assertion width | 5T-10 min | +-------+---------------------------------------+---------------+ | T13 | HP_DATAEN assertion to HP_AS | T+15 max | | | deassertion | | +-------+---------------------------------------+---------------+ | T14 | Data hold time after HP_DATAEN | T-15 min | | | deassertion | | +-------+---------------------------------------+---------------+ | T15 | address hold time after HP_ADREN | 0 | | | deassertion | | +-------+---------------------------------------+---------------+ 12.2 Microprocessor Write Cycles When the microprocessor wishes to modify the contents of an SII register, it asserts HP_CS. Upon detection of this signal, the SII will finish any memory transaction currently in progress and service the microprocessor. The time that can elapse during this period is variable; it depends greatly on the memory bus activity. In the best case (the memory port is idle), the assertion of HP_ADREN could be as soon as 100 ns. following the assertion of HP_CS. In the worst case (the SII has just begun a new memory cycle), the microprocessor is forced to sit idle as the SII asserts HP_ AS, followed by HP_DS to the memory. The duration of this action is a function of memory bandwidth and SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 81 External Operations and Timing 19 January 1987 traffic and will not be estimated here. Before the assertion of HP_ADREN, the SII will release the HP_WRITE signal, preparing for the microprocessor access. Upon the assertion of HP_ADREN, the external logic must begin to drive the register address onto the HP_DAL lines and also drive HP_WRITE. At this time, the external logic can deassert HP_CS. One HP_CLK cycle following the assertion of HP_ADREN, the SII will assert HP_AS. This does not require any reaction by the external logic. This does not happen in the arbitrating mode. Two clock cycles later, the SII will deassert HP_ADREN, thereby ending the address portion of the cycle. The SII will latch the contents of the HP_DAL lines internally, along with the HP_WRITE signal. Three clock cycles later, the SII will assert the HP_DATAEN signal. The external logic may drive the contents of the selected register onto the HP_DAL lines. One clock cycle later, the SII will deassert HP_AS. This signals the external logic to release HP_WRITE, if it hasn't done so already. Two clock cycles later, the SII will deassert the HP_DATAEN signal, thereby ending the cycle. Data will be latched into the SII upon the deassertion of HP_ DATAEN. No hold time is required by the SII. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 82 External Operations and Timing 19 January 1987 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HP_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ (input) | | | | | |T1 | | | | HP_WRITE L----|-\_________|__/________|___________|__/---------------- | | ||T2 | | ___ | _|_|_________|___________|___________________ HP_CS L |\__|_________/_|_|_________|___________|_______________/ (input) | | | | | | | | | |T4 | |T5 | | | T3 | | | | | | | | | _________ __________|___________|__________________ HP_ADREN L |\_________/| | | (output) | | | | | | T6 | | |T8 | | | | | | |T9 | | T7 | | | _________________________________ __________________ HP_DATAEN L | | |\_________/| (output) | | | | |T10| | | T11 | ______________ | | ________|_________________ HP_AS L |\__________________|__/| | (output) | | | | | | | |T13| | | T12 | |T14| | | | | | T15 | | _________ | _________ | | ____________ HP_DAL H _________< ADDRESS >_________< DATA IN >____________ (BiD) Times are as follows: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 83 External Operations and Timing 19 January 1987 +-------+---------------------------------------+---------------+ | Name | Description | Time | +-------+---------------------------------------+---------------+ | T1 | HP_CLK cycle time | T (50 ns. min)| +-------+-------------------------------------------------------+ | T2 | HP_WRITE hold time following HP_ADREN | 0 | | | deassertion | | +-------+---------------------------------------+---------------+ | T3 | HP_CS assertion to HP_ADREN assertion| no max | +-------+-------------------------------------------------------+ | T4 | HP_CLK rising to HP_ADREN assertion | 41 ns min | +-------+-------------------------------------------------------+ | T5 | HP_CLK rising to HP_ADREN deassertion | 38 ns min | +-------+---------------------------------------+---------------+ | T6 | HP_ADREN assertion width | 3T-10 min | +-------+---------------------------------------+---------------+ | T7 | HP_ADREN deassertion to HP_DATAEN | 3T-5 min | | | assertion | | +-------+---------------------------------------+---------------+ | T8 | HP_CLK rising to HP_DATAEN assertion | 41 ns min | +-------+---------------------------------------+---------------+ | T9 |HP_CLK rising to HP_DATAEN deassertion | 38 ns min | +-------+---------------------------------------+---------------+ | T10 | HP_ADREN assertion to HP_AS assertion | T min | +-------+---------------------------------------+---------------+ | T11 | HP_DATAEN assertion width | 3T-10 min | +-------+---------------------------------------+---------------+ | T12 | HP_AS assertion width | 5T-10 min | +-------+---------------------------------------+---------------+ | T13 | HP_DATAEN assertion to HP_AS | T+15 max | | | deassertion | | +-------+---------------------------------------+---------------+ | T14 | Data hold time after HP_DATAEN | 0 | | | deassertion | | +-------+---------------------------------------+---------------+ | T15 | address hold time after HP_ADREN | 0 | | | deassertion | | +-------+---------------------------------------+---------------+ 12.3 Memory Read Cycles (Normal Mode) When the SII wishes to begin a new transfer, it places the address of the memory location onto the HP_DAL lines. Two clock cycles later, HP_AS is asserted. This indicates to the external logic that the SII is beginning a new cycle. The external logic must latch the address on the asserting edge of HP_AS. Two clock cycles later, the SII will withdraw the address from the multiplexed bus. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 84 External Operations and Timing 19 January 1987 Two clock ticks later, the SII will assert HP_DS. This signals that the SII wishes to read a memory location. This pulse will last a minimum of 200 ns., although it can be made longer. The SII monitors the HP_RDY signal waiting for its assertion. Once this is seen, the SII is free to end the current HP_DS. Following the deassertion of the first data strobe, the SII will deassert HP_AS. For each additional contiguous word the SII needs, it will assert only HP_DS. (The HP_AS signal is used to select a new starting address and is not needed on a per access basis.) If the microprocessor wishes to access an SII register while a DMA operation is in progress, the SII will finish the data strobe currently asserted and service the microprocessor. Following this, the SII will NOT issue a new address strobe and will expect the external logic to continue from the address which was last read. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYS_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ (input) |T1 | | | | | | |T2| | | ______| | | ____________________________ HP_AS L |\_______|_______________|___/ (output) | | | | T3 | T4 | | | | |_|______ | __________________ HP_DAL H< ADDRESS >_|______< DATA IN >__________________< DATA IN (BiD) | | |T7| | |T5 | | _________________ | T6 |_____________________ HP_DS L \______________/ \_________ | | T8 | | T9 | ________________________________|_______________________________ HP_WRITE L | | (output) | | T10 | |T11 | ______________________ ________________________________ HP_RDY \________/ (input) Times are as follows: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 85 External Operations and Timing 19 January 1987 +-------+-----------------------------------------------+-------+ | Name | Description | Time | +-------+-----------------------------------------------+-------+ | T1 | SYS_CLK cycle time | 50 ns | +-------+-----------------------------------------------+-------+ | T2 | SYS_CLK rising to HP_AS assertion (max) | 61 ns | +-------+-----------------------------------------------+-------+ | T3 | Address Valid to HP_AS assertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T4 | Address Hold after HP_AS assertion (min)| 75 ns | +-------+-----------------------------------------------+-------+ | T5 | SYS_CLK rising to HP_DS assertion (max) | 54 ns | +-------+-----------------------------------------------+-------+ | T6 | Data setup to HP_DS deassertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T7 | Data hold after HP_DS deassertion (min) | 0 ns | +-------+-----------------------------------------------+-------+ | T8 | Data Strobe deassertion time (minimum) | 245 ns| +-------+-----------------------------------------------+-------+ | T9 | Data Strobe assertion time (minimum) | 195 ns| +-------+-----------------------------------------------+-------+ | T10 | HP_RDY assertion to HP_DS deassertion (min) | 100 ns| +-------+-----------------------------------------------+-------+ | T10 | HP_RDY assertion to HP_DS deassertion (max)* | 170 ns| +-------+-----------------------------------------------+-------+ | T11 | HP_RDY assertion after HP_DS assertion | 90 ns | | | to insure 500 ns. cycle time (max) | | +-------+-----------------------------------------------+-------+ * If HP_RDY is asserted within the first 90 ns. of HP_DS, the data strobe will be 250 ns. long. The timing parameter, T10, refers to the synchronization delay if HP_RDY is NOT asserted within the first 90 ns. 12.4 Memory Write Cycles (Normal Mode) When the SII wishes to begin a new transfer, it places the address of the memory location onto the HP_DAL lines. Two clock cycles later, HP_AS is asserted. This indicates to the external logic that the SII is beginning a new cycle. The external logic must latch the address on the asserting edge of HP_AS. Two clock cycles later, the SII will withdraw the address from the multiplexed bus. Two clock ticks later, the SII will assert HP_DS. This signals that the SII has placed the data onto the DAL lines. This pulse will last a minimum of 200 ns., although it can be made longer. The SII monitors the HP_RDY signal waiting for its SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 86 External Operations and Timing 19 January 1987 assertion. Once this is seen, the SII is free to end the current HP_DS. Following the deassertion of the first data strobe, the SII will deassert HP_AS. For each additional contiguous word the SII needs, it will assert only HP_DS. (The HP_AS signal is used to select a new starting address and is not needed on a per access basis.) If the microprocessor wishes to access an SII register while a DMA operation is in progress, the SII will finish the data strobe currently asserted and service the microprocessor. Following this, the SII will NOT issue a new address strobe and will expect the external logic to continue from the address which was last written. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYS_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ (input) |T1 | | | | | | |T2| | | ______| | | ____________________________ HP_AS L |\_______|_______________|___/ (output) | | | | T3 | T4 | | | | |_|______ | __________________ HP_DAL H< ADDRESS >_|______< DATA OUT >__________________< DATA OU (BiD) | | |T7| | |T5 | | _________________ | T6 |_____________________ HP_DS L \______________/ \_________ | | T8 | | T9 | | | HP_WRITE L_______________|______________|_______________________________ (output) | | T10 | |T11 | ______________________ ________________________________ HP_RDY \________/ (input) Times are as follows: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 87 External Operations and Timing 19 January 1987 +-------+-----------------------------------------------+-------+ | Name | Description | Time | +-------+-----------------------------------------------+-------+ | T1 | SYS_CLK cycle time | 50 ns | +-------+-----------------------------------------------+-------+ | T2 | SYS_CLK rising to HP_AS assertion (maximum) | 61 ns | +-------+-----------------------------------------------+-------+ | T3 | Address Valid to HP_AS assertion (minimum) | 75 ns | +-------+-----------------------------------------------+-------+ | T4 | Address Hold after HP_AS assertion (minimum) | 75 ns | +-------+-----------------------------------------------+-------+ | T5 | SYS_CLK rising to HP_DS assertion (maximum) | 54 ns | +-------+-----------------------------------------------+-------+ | T6 | Data setup to HP_DS deassertion (minimum) | 75 ns | +-------+-----------------------------------------------+-------+ | T7 | Data hold after HP_DS deassertion (minimum) | 40 ns | +-------+-----------------------------------------------+-------+ | T8 | Data Strobe deassertion time (minimum) | 245 ns| +-------+-----------------------------------------------+-------+ | T9 | Data Strobe assertion time (minimum) | 195 ns| +-------+-----------------------------------------------+-------+ | T10 | HP_RDY assertion to HP_DS deassertion (min) | 100 ns| +-------+-----------------------------------------------+-------+ | T10 | HP_RDY assertion to HP_DS deassertion (max)* | 170 ns| +-------+-----------------------------------------------+-------+ | T11 | HP_RDY assertion after HP_DS assertion | 90 ns | | | to insure 500 ns. cycle time (max) | | +-------+-----------------------------------------------+-------+ * If HP_RDY is asserted within the first 90 ns. of HP_DS, the data strobe will be 250 ns. long. The timing parameter, T10, refers to the synchronization delay if HP_RDY is NOT asserted within the first 90 ns. 12.5 Memory Read Cycles (Arbitrating Mode) When the SII wishes to begin a new transfer, it places the address of the memory location onto the HP_DAL lines. At the same time, the HP_ADDR16 (LOAD) signal is asserted. Two clock cycles later, HP_AS (CTRCLK) is asserted to load the counter. Two clock cycles later, the SII will withdraw the address from the multiplexed bus and deassert LOAD. Two clock ticks later, the SII will assert HP_DS. This signals that the SII wishes to read a memory location. This pulse will last 200 ns. SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 88 External Operations and Timing 19 January 1987 One hundred and fifty ns. after the assertion of HP_DS, the SII will deassert CTRCLK. Fifty ns. following the deassertion of the data strobe, the SII will assert HP_AS (CTRCLK) to increment the counter. This pulse is asserted until 150 ns. after the assertion of the following HP_DS. For each additional contiguous word the SII needs, it will assert only HP_DS and CTRCLK. If the microprocessor wishes to access an SII register while a DMA operation is in progress or an external device requests the SII memory bus, the SII will finish the data strobe currently in progress and service the request. Following this, the SII will NOT issue a new load strobe and will expect the external logic to continue from the address which was last read. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYS_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ (input) | | T1| | | | |T2 | | ______ | _____|____________________________________ HP_ADDR16 |\____|_________/ | (output) | | | | | | | | | | |T3 | | | T4 | T5 | | _____________|_____________ ______________ HP_AS _____________/ | \_______/ (output) | | | | T13 | | | |T6 ______________|_______________ ___________ HP_DS L | \______________/| |\______ | | | T12 | | T8 | T9 | | T10 | |T7 | | | T11 | | _____ _________ | |_______________ HP_DAL H_____< ADDRESS >_________< DATA IN >_______________ (BiD) ________________________________________________________________ HP_WRITE L (output) Times are as follows: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 89 External Operations and Timing 19 January 1987 +-------+-----------------------------------------------+-------+ | Name | Description | Time | +-------+-----------------------------------------------+-------+ | T1 | SYS_CLK cycle time | 50 ns | +-------+-----------------------------------------------+-------+ | T2 | SYS_CLK rising to HP_ADDR16 assertion (max) | 61 ns | +-------+-----------------------------------------------+-------+ | T3 | SYS_CLK rising to HP_AS assertion (max) | 70 ns | +-------+-----------------------------------------------+-------+ | T4 | HP_ADDR16 assertion to HP_AS assertion (min) | 90 ns | +-------+-----------------------------------------------+-------+ | T5 | HP_ADDR16 hold after HP_AS assertion (min) | 90 ns | +-------+-----------------------------------------------+-------+ | T6 | SYS_CLK rising to HP_DS assertion (max) | 54 ns | +-------+-----------------------------------------------+-------+ | T7 | Data hold time after HP_DS deassertion (min) | 0 ns | +-------+-----------------------------------------------+-------+ | T8 | Address Valid to HP_AS assertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T9 | Address Hold after HP_AS assertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T10 | Data Strobe assertion time (min) | 195 ns| +-------+-----------------------------------------------+-------+ | T11 | Data setup time to HP_DS deassertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T12 | Data Strobe deassertion time (minimum) | 95 ns | +-------+-----------------------------------------------+-------+ | T13 | HP_AS deassertion time (min) | 90 ns | +-------+-----------------------------------------------+-------+ 12.6 Memory Write Cycles (Arbitrating Mode) When the SII wishes to begin a new transfer, it places the address of the memory location onto the HP_DAL lines. At the same time, HP_ADDR16 (LOAD) is asserted. Two clock cycles later, HP_AS (CTRCLK) is asserted to clock the new address into the counter. Two clock cycles later, the SII will withdraw the address from the multiplexed bus and deassert LOAD. Two clock ticks later, the SII will assert HP_DS. This signals that the SII has placed the data onto the DAL lines. This pulse will last 200 ns. One hundred and fifty ns. after the assertion of HP_DS, the SII will deassert CTRCLK. Fifty ns. following the deassertion of the data strobe, the SII will assert HP_AS (CTRCLK) to increment the counter. This pulse is asserted until 150 ns. after the assertion of the SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 90 External Operations and Timing 19 January 1987 following HP_DS. For each additional contiguous word the SII writes, it will assert only HP_DS and CTRCLK. If the microprocessor wishes to access an SII register while a DMA operation is in progress or an external device requests the SII bus, the SII will finish the data cycle currently in progress and service the request. Following this, the SII will NOT issue a new load strobe and will expect the external logic to continue from the address which was last written. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYS_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ (input) | | T1| | | | |T2 | | ______ | _____|____________________________________ HP_ADDR16 |\____|_________/ | (output) | | | | | | | | | | |T3 | | | T4 | T5 | | _____________|_____________ ______________ HP_AS _____________/ | \_______/ (output) | | | | T13 | | | |T6 ______________|_______________ ___________ HP_DS L | \______________/| |\______ | | | T12 | | T8 | T9 | | T10 | |T7 | | | T11 | | _____ _________ | |_______________ HP_DAL H_____< ADDRESS >_________< DATA OUT >_______________ (BiD) HP_WRITE L______________________________________________________________ (output) Times are as follows: SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 91 External Operations and Timing 19 January 1987 +-------+-----------------------------------------------+-------+ | Name | Description | Time | +-------+-----------------------------------------------+-------+ | T1 | SYS_CLK cycle time | 50 ns | +-------+-----------------------------------------------+-------+ | T2 | SYS_CLK rising to HP_ADDR16 assertion (max) | 61 ns | +-------+-----------------------------------------------+-------+ | T3 | SYS_CLK rising to HP_AS assertion (max) | 70 ns | +-------+-----------------------------------------------+-------+ | T4 | HP_ADDR16 assertion to HP_AS assertion (min) | 90 ns | +-------+-----------------------------------------------+-------+ | T5 | HP_ADDR16 hold after HP_AS assertion (min) | 90 ns | +-------+-----------------------------------------------+-------+ | T6 | SYS_CLK rising to HP_DS assertion (max) | 54 ns | +-------+-----------------------------------------------+-------+ | T7 | Data hold time after HP_DS deassertion (min) | 40 ns | +-------+-----------------------------------------------+-------+ | T8 | Address Valid to HP_AS assertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T9 | Address Hold after HP_AS assertion (min) | 75 ns | +-------+-----------------------------------------------+-------+ | T10 | Data Strobe assertion time (min) | 195 ns| +-------+-----------------------------------------------+-------+ | T11 | Data setup time to HP_DS deassertion (min) | 0 ns | +-------+-----------------------------------------------+-------+ | T12 | Data Strobe deassertion time (minimum) | 95 ns | +-------+-----------------------------------------------+-------+ | T13 | HP_AS deassertion time (min) | 90 ns | +-------+-----------------------------------------------+-------+ SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 92 Implementation Guidelines 19 January 1987 13 IMPLEMENTATION GUIDELINES In order for the SII to operate at its peak transfer rate, it must be able to access memory immediately upon request. Any delays for arbitration, hold-offs, etc. can have a serious impact on performance. The SII has minimal buffering internally, a total of five bytes in all. This means the SII is very sensitive to its backport throughput. The following is a simplified model of the data movement inside the SII for a memory write operation: 1. A byte is moved from the FIFO to the word builder. 2. Wait for new data to be ready. 3. A second byte is moved to the word builder. 4. The word is stored in memory. While the word is being stored, the SII data mover does not operate. Therefore, the time taken to store the word is actually idle time inside the SII. However, during this time, new data bytes may be sent by the remote device. A three byte FIFO is enough to handle this in the normal case. The problem arises when the FIFO is full and the traffic across the SCSI bus becomes throttled. The time to empty the FIFO and resume normal operation can be as much as 500-1000 nanoseconds. Obviously, if this happens frequently, performance will suffer severely. There are ways to avoid this problem. The list below describes some of these options. o Arbitrating mode 1. The number of BUS_REQs should be minimal. If possible, accesses should be done while the SII is idle. 2. If the external cycles are kept short (~150 ns.), they may be done during the "dead" time of the SII. This is possible since, in arbitrating mode, the HP_DS is shorter so the amount of SII "dead" time increases. o Normal mode 1. The goal of the implementor should be to maintain a 4 MB/s bandwidth on the SII memory bus. This requires 500 ns. cycle times. Since the SII specifies a minimum HP_DS deassertion time of 250 ns., the HP_DS assertion time must not exceed 250 ns. To guarantee this, HP_RDY SII Specification - Rev 1.3 FOR INTERNAL USE ONLY Page 93 Implementation Guidelines 19 January 1987 should be returned within 90 ns. after the assertion of HP_DS. APPENDIX A SII PINOUT SII PINOUT Page A-2 19 January 1987 The following is the current pinout for the SII chip. It is currently packaged in a 68 pin grid array. 68+ 67+ 65+ 63+ 61+ 59+ 57+ 55+ 53+ 2+ 1+ 66+ 64+ 62+ 60+ 58+ 56+ 54+ 52+ 51+ 4+ 3+ o 49+ 50+ 6+ 5+ 47+ 48+ 8+ 7+ 45+ 46+ 10+ 9+ 43+ 44+ 12+ 11+ 41+ 42+ 14+ 13+ 39+ 40+ 16+ 15+ 37+ 38+ 17+ 18+ 20+ 22+ 24+ 26+ 28+ 30+ 32+ 35+ 36+ 19+ 21+ 23+ 25+ 27+ 29+ 31+ 33+ 34+ Top View SII PINOUT Page A-3 19 January 1987 The pin names are as follows: 1. SP_DATA<1> H 35. HP_DAL<15> H 2. SP_DATA<2> H 36. HP_ADDR16 H 3. SP_DATA<3> H 37. HP_WRITE L 4. SP_DATA<4> H 38. HP_AS L 5. SP_DATA<5> H 39. HP_DS L 6. SYS_TEST L 40. HP_BUSGRANT L 7. SYS_CLK H 41. HP_DAL<00> H 8. VDD 42. VDD 9. GND 43. GND 10. SP_DATA<6> H 44. HP_DAL<01> H 11. SP_DATA<7> H 45. HP_DAL<02> H 12. SP_PARITY H 46. HP_DAL<03> H 13. SP_CMD H 47. HP_DAL<04> H 14. SP_MSG H 48. HP_DAL<05> H 15. SP_SELOUT H 49. HP_DAL<06> H 16. SP_TGS H 50. HP_DAL<07> H 17. SP_INPUT H 51. HP_DAL<08> H 18. GND 52. GND 19. SP_REQ H 53. HP_DAL<09> H 20. SP_ACK H 54. HP_DAL<10> H 21. SP_ARB H 55. HP_DAL<11> H 22. SP_ATN H 56. HP_DAL<12> H 23. SP_SBEN L 57. HP_DAL<13> H 24. SP_IGS H 58. HP_DAL<14> H 25. VDD 59. VDD 26. GND 60. GND 27. SP_SELIN H 61. HP_CLK H 28. SP_BSYIN H 62. HP_CS L 29. SP_BSYOUT H 63. HP_RDY L 30. SP_RSTIN H 64. HP_ADREN L 31. SP_RSTOUT L 65. HP_DATAEN L 32. SP_ID<0> L 66. SYS_INT L 33. SP_ID<1> L 67. SYS_RESET L 34. SP_ID<2> L 68. SP_DATA<0> H APPENDIX B DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE B.1 INTRODUCTION This appendix presents some implementation models for the diagnostics of the SII. These are by no means a comprehensive set and can be added to. The algorithms presented here demonstrate a possible test procedure for the SII. B.2 EXTERNAL LOOPBACK TESTING (LOOPED CONNECTOR) This test simply checks the SII SCSI drivers, the connection to the Receiver/Driver chip, the SCSI bus receivers and drivers. This test only exercises a small percent of the SII. This test makes use of a loop-back connector. This loop-back connector should be configured as follows: PARITY ties to BSY DATA<7> ties to SEL DATA<6> ties to RST DATA<5> ties to ACK DATA<4> ties to REQ DATA<3> ties to ATN DATA<2> ties to MSG DATA<1> ties to C/D DATA<0> ties to I/O This configuration allows values written into the SDB/SC1 to be read in the same bit positions in the other register. This test should proceed as follows: 1. Verify the DIA bit in the CSR is set. 2. Set the following bits in SC2: SBE 3. Write various patterns to the SDB. These patterns should be readable in both the SC1 and SDB registers. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-2 19 January 1987 4. Set the following bits in SC2: None 5. Write various patterns to bits BSY,SEL, and RST in the SC1. These patterns should be reflected in the PARITY,DATA<7> and DATA<6> bits of the SDB, as well as in the SC1. The other bits in both of these registers should read as zero. 6. Set the following bits in SC2: IGS 7. Write various patterns to ACK and ATN in the SC1. These patterns should be reflected in DATA<5> and DATA<3> of the SDB, as well as in the SC1 register. The other bits in both of these registers should read as zero. 8. Set the following bits in SC2: TGS 9. Write various patterns to C/D,I/O,MSG, and REQ in the SC1. These patterns should be reflected in bits DATA<4>, DATA<2>, DATA<1> and DATA<0> of the SDB register. The other bits in both of these registers should read as zero. 10. Set the following bits in SC2: ARB 11. Write the SDB register to 01FFH. Read the SDB register. There should be only one bit asserted. The bit significant position of this single bit should agree with the value in the ID register. 12. Vary the ID of the chip (see ID register description). The value read in the SDB should change accordingly (i.e. the number 2 raised to the ID should appear in the SDB). In other words, if the ID of the chip were 5, the SDB register should read 020H. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-3 19 January 1987 B.3 INTERNAL LOOP AROUND TESTING This section describes the internal loop-back testing which can be done with the help of diagnostic 'hooks' provided in the SII. The following examples serve only as a template; implementations may choose other methods of testing. B.3.1 Target Testing In this mode, the SII is to function as the target, and the local processor is to be the initiator. The processor will "select" the SII, transfer the required command bytes, follow with the required data bytes and then receive the status byte from the SII. Three subroutines are defined in this section, one to send a command byte, another to send a data byte, and the third to receive the status byte. They are described below. SendCommByte(CommByte) /* The only parameter is the command byte to be sent */ word CommByte; { begin { Read SC1 /* This register contains the control signals the SII uses on the SCSI bus. */ /* * We are waiting for the SII to assert REQ in the command phase. * It may be advisable to set a software timer to avoid being * here forever. */ While (SC1 != 132H) do Read SC1 /* * Once REQ is asserted, we can present the data to the SII. After * writing the data, we will assert ACK, signaling that the data * is available. */ Write CommByte into SDB Write 132H into SC1 /* * We now wait for the SII to accept the byte. This is done by * its deassertion of REQ. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-4 19 January 1987 */ While (SC1 != 102H) do Read SC1 /* * Now deassert ACK and we're done. */ Write 102H into SC1 /* * The byte has now been delivered to the SII. */ } } SendDataByte(DataByte) /* The only parameter is the data byte to be sent */ word DataByte; { begin { Read SC1 /* This register contains the control signals the SII uses on the SCSI bus. */ /* * We are waiting for the SII to assert REQ in the data phase. * It may be advisable to set a software timer to avoid being * here forever. */ While (SC1 != 130H) do Read SC1 /* * Once REQ is asserted, we can present the data to the SII. After * writing the data, we will assert ACK, signaling that the data * is available. */ Write DataByte into SDB Write 130H into SC1 /* * We now wait for the SII to accept the byte. This is done by * its deassertion of REQ. */ While (SC1 != 100H) do DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-5 19 January 1987 Read SC1 /* * Now deassert ACK and we're done. */ Write 100H into SC1 /* * The byte has now been delivered to the SII. */ } } GetStatusByte() /* This routine gets status byte from the SII */ { begin { /* * Wait for SII to assert REQ in status phase */ While (SC1 != 133H) do Read SC1. /* * Status is ready in SDB register. * Let's get it. */ Read byte from SDB into StatusByte. /* * Now assert ACK to acknowledge byte */ Write 133H to SC1 /* * Wait for SII to deassert REQ */ While (SC1 != 103H) do Read SC1 /* * Now deassert ACK */ DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-6 19 January 1987 Write 103H to SC1 /* * Return status byte */ Return(StatusByte); } } These three subroutines are used in the transmission of data from the processor to the SII. The main routine to be used is described below. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-7 19 January 1987 Target() { begin { /* First we must set up the proper data structure in memory for * the SII to receive data into. Refer to DSSI mode for * further definition of these fields. Remember Buffer must be on * a quad word boundary. */ word Buffer[100]; Write 0 into Buffer[0] /* this is last buffer */ Write 0 into Buffer[1] /* clear the status word */ Write 8000H into Buffer[2] /* interrupt when thru */ /* * Memory is now set up. Let's point the SII short target list * pointer to this structure. */ Shift Address of Buffer[0] right 2 places. Write this value into STLP. /* * Now that the SII is set up, let's define the data structures * that the microprocessor will need. Refer to the DSSI datalink * specification for further definition of these bytes. */ word CommandBytes[7]; word DataBytes[11]; CommandBytes[0] = 1E1H;/* This is DSSI datalink opcode. Note */ /* this is a short buffer */ CommandBytes[1] = 100H;/* This is the flag byte. Note that */ /* the ReqAck offset must be zero for */ /* loopback to work. */ CommandBytes[2] = 007; /* This is the destination port. */ /* This must match the ID of the SII */ CommandBytes[3] = 100H;/* This is the source port. */ /* This must match the ID that the */ /* SII thinks selected it. */ CommandBytes[4] = 10AH;/* This is the number of data bytes */ /* that we are sending */ CommandBytes[5] = 100H;/* This is the most significant byte */ /* of the length. */ CommandBytes[6] = 0ECH;/* The checksum of the command bytes */ DataBytes[0] = 1FFH; /* Various data pattern to test the SII */ DataBytes[1] = 100H; DataBytes[2] = 155H; DataBytes[3] = 1AAH; DataBytes[4] = 10FH; DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-8 19 January 1987 DataBytes[5] = 1F0H; DataBytes[6] = 1A5H; DataBytes[7] = 15AH; DataBytes[8] = 100H; DataBytes[9] = 1FFH; DataBytes[10] = 1FFH; /* Checksum of the previous 10 bytes */ /* * Note that bit 8 of the above bytes is the odd parity. */ /* * Now to begin the operation. We will set up some SII registers * correctly. The DICTRL,CSR and ID registers must be properly * initialized. */ /* * Put chip in loopback mode. */ Write 8 into the DICTRL register. /* * Enable selections and parity checking */ Write 6 into the CSR register. /* * Set up ID of the chip. */ Write 8007H into the ID register. /* * Note the ID register is set to 7. This is not a requirement. * However, if it is different, the command byte must be modified * as well as the selection pattern. * */ /* * Let's get started. First, we will enable DSSI mode in the SII. * Then, we will select the SII and transfer the data. * */ Write 80FFH into the DSCTRL register. /* SII is enabled */ /* * Note that all devices are DSSI devices. */ DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-9 19 January 1987 Write 181H into the SDB register. /* This is the selection */ /* for device 0 selecting */ /* device 7. Refer to SCSI */ /* spec for more detail. */ Write 80H into SC1 register. /* We assert the SEL signal so */ /* the SII realizes this is a */ /* selection. */ /* Now we wait for the SII to respond to the selection. This * is signified by the SII returning BSY. We will poll SC1 * until this is set. */ While (SC1 != 102H) do Read SC1 Register. /* * Now deassert SEL, set BSY and proceed with the transfer. */ Write 102H into SC1 /* * First the command bytes (Command phase) */ for (i=0,i<7,i++) do SendCommByte(CommandBytes[i]); /* * Now the data bytes (Data phase) * First, make sure SII enters DATA OUT. */ While (SC1 != 100H) do Read SC1 Register. /* * Now write phase back to SII. */ Write 100H to SC1. for (i=0,i<0AH,i++) do SendDataByte(DataBytes[i]); /* * Now let's receive the status (Status phase) */ /* * First, make sure SII enters STATUS IN. */ DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-10 19 January 1987 While (SC1 != 103H) do Read SC1 Register. /* * Now write phase back to SII. */ Write 103H to SC1. Status = GetStatusByte(); Check if Status is the expected value (ACK or NAK). /* * Wait for SII to disconnect. */ While (SC1 == 103H) do Read SC1 Write 0 into SC1. /* * Transfer is all over now. * Let's check the status in the buffer now. * The second word in the buffer should read 8000H */ Check that Buffer[1] is 8000H Verify that the correct data appears in the buffer. } } This procedure can be modified to verify the error-checking capabilities of the SII chip as a target. Several variations of this procedure will be enumerated and the differences in code included. - Use of both lists - The above mentioned procedure should be repeated using a long buffer to verify that functionality using the LTLP. This is done by setting up the LTLP and appropriate data structures in memory and changing the first command byte to 0E0H and modifying the command phase checksum accordingly. The remainder of the procedure remains the same. Using the STLP and LTLP to point to the low end as well as the high end of the buffer memory also provides additional coverage, as well as exercising the entire set of address lines. - Comm Error - the SII checks the incoming command opcode to insure that bits 7-5 are all 1. This field is in the first byte. See DSSI Data Link Specification for more detail. If these bits are not all 1, the SII will receive a second command byte and then continue with the Status byte, DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-11 19 January 1987 returning NACK (negative acknowledgment). Buffer[1] should read 8002H. - Destination Error - the SII checks the lower three bits of the incoming destination port as sent in the packet with its own ID. This information appears in the third command byte. See DSSI Data Link Specification for more detail. If these two values do not match, the SII will switch to Status phase after receiving this byte and deliver a NACK (negative acknowledgment). Buffer[1] should read 8002H. - Source Error - the SII checks the lower three bits of the incoming source port as sent in the packet with its SLCSR register. This information appears in the fourth command byte. See DSSI Data Link Specification for more detail. If these two values do not match, the SII will switch to Status phase after receiving this byte and deliver a NACK (negative acknowledgment). Buffer[1] should read 8002H. - No Available Buffer - If the SII has no available input buffers, it aborts the transfer after receiving one command byte and returns a NACK (negative acknowledgment) in Status phase. This can be done by setting up the memory data structures as shown above except for the following change: Write 8000H into Buffer[1] The SII will receive the first command byte and then switch to Status phase. Nothing will be written into memory. - RSTIN asserted during Status Phase - Follow the procedure detailed above until Status phase is reached. Once the SII has signaled that the status byte is ready (i.e. REQ is asserted), assert RST in SC1. Now clear the SC1 register. The buffer should appear correctly, except the status, Buffer[1], will read 8080H. The appropriate bits should be checked in the CSTAT register as well. - RSTIN asserted before Status Phase - Similar to the previous test, except RSTIN is asserted before reaching Status phase. In this case, the SII will abort the transfer, leaving no status in memory. Follow the procedure detailed above until Data phase. Now assert RST in SC1. Then clear the SC1 register. The buffer will show any data that was transferred (i.e. command bytes), however, the status word, Buffer[1] will be clear. - Checksum Error - Follow the procedure detailed above until the seventh byte of the command phase. Replace the checksum, 0ECH, with another value (any other number will do). After receiving this byte, the SII will switch to Status phase and return a NAK (negative acknowledgment). The other variation of this is to corrupt the data checksum (leaving the command one intact). Buffer[1] should read DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-12 19 January 1987 8020H. - Parity Error - Follow the above detailed procedure, with the following change. Replace one byte's parity bit with its complement. This can be done in either the Command or Data phase. After receiving that byte, the SII will switch to Status phase and return NAK (negative acknowledgment). Buffer[1] should read 8001H. - Selected with ATN - This test emulates a DSSI initialization sequence. After the DSCTRL register is set up, the following should be done: /* * Write SDB register. This is the selection pattern for device * 0 selecting device 7. Refer to SCSI spec for more detail. */ Write 181H into the SDB register. /* * Assert SEL signal so that the SII realizes that this is a * selection. We also assert ATN. */ Write 88H into SC1 register. /* Now we wait for the SII to respond to the selection. This * is signified by the SII returning BSY. We will poll SC1 * until this is set. */ While ((SC1 & 100H) != 100H) do Read SC1 Register. /* * Now deassert SEL, set BSY and proceed with the transfer. */ Write 100H into SC1 At this point, the CSTAT and DSCTRL registers should be read. The CSTAT register should read 84F8H. The DSCTRL register should have the DSA bit cleared now. At this point, either SCSI commands can be attempted or the chip can be reset. Nothing should be written to memory. - Selected by non-DSSI device - The effect of this is almost the same as a select with ATN. Begin by writing the DSCTRL register to 8000H. Follow this by writing 181H into the SDB register and then 80H into the SC1 register. The DSA bit in DSCTRL should now be cleared. The CSTAT should read 84F0H. Nothing should be written to memory. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-13 19 January 1987 B.3.2 Initiator Testing In this mode, the SII is to function as the initiator, and the local processor is to be the target. The processor will be "selected" by the SII, receive the required command bytes, follow with the required data bytes and then send the status byte to the SII. Three subroutines are defined in this section, one to receive a command byte, another to receive a data byte, and the third to send the status byte. They are described below. GetCommByte() { begin { Read SC1 /* This register contains the control signals the SII uses on the SCSI bus. */ /* * We are waiting for the SII to assert REQ in the command phase. * It may be advisable to set a software timer to avoid being * here forever. */ While (SC1 != 132H) do Read SC1 /* * Once REQ is asserted, we can read the data from the SII. After * reading the data, we will assert ACK, signaling that the data * has been taken. */ Read byte from SDB into CommByte. Write 132H into SC1 /* * We now wait for the SII to deassert REQ. */ While (SC1 != 102H) do Read SC1 /* * Now deassert ACK and we're done. */ Write 102H into SC1 /* * The byte has now been delivered by the SII. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-14 19 January 1987 * Return the value */ Return(CommByte); } } GetDataByte() { begin { Read SC1 /* This register contains the control signals the SII uses on the SCSI bus. */ /* * We are waiting for the SII to assert REQ in the data phase. * It may be advisable to set a software timer to avoid being * here forever. */ While (SC1 != 130H) do Read SC1 /* * Once REQ is asserted, we can read the data from the SII. After * reading the data, we will assert ACK, signaling that the data * has been taken. */ Read byte from SDB into DataByte. Write 130H into SC1 /* * We now wait for the SII to deassert REQ. */ While (SC1 != 100H) do Read SC1 /* * Now deassert ACK and we're done. */ Write 100H into SC1 /* * The byte has now been delivered by the SII. * Let's return the value */ DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-15 19 January 1987 Return(DataByte); } } SendStatusByte(StatusByte) /* This routine gives status to the SII */ word StatusByte; { begin { /* * Wait for SII to assert REQ in status phase */ While (SC1 != 133H) do Read SC1. /* * Once REQ is asserted, we can present the data to the SII. After * writing the data, we will assert ACK, signaling that the data * is available. */ Write StatusByte into SDB Write 133H into SC1 /* * We now wait for the SII to accept the byte. This is done by * its deassertion of REQ. */ While (SC1 != 103H) do Read SC1 /* * Now deassert ACK */ Write 103H to SC1 } } These three subroutines are used in the transmission of data from the SII to the processor. The main routine to be used is described below. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-16 19 January 1987 Initiator() { begin { /* First we must set up the proper data structure in memory for * the SII to send data out from. Refer to DSSI mode for * further definition of these fields. Remember Buffer must be on * a quad word boundary. */ word Buffer[100]; Buffer[0] = 0; /* this is last buffer */ Buffer[1] = 0; /* clear the status word */ Buffer[2] = 8000H; /* interrupt when thru, select 0 */ Buffer[3] = 00E1H; /* E1H and 00H are first two comm bytes */ Buffer[4] = 0700H; /* 00H and 07H are third and fourth bytes */ Buffer[5] = 000AH; /* 10 bytes of data coming */ Buffer[6] = 000AH; /* Next segment has 10 bytes, no link */ Buffer[7] = address of Buffer[8] shifted right 2 places; Buffer[8] = 00FFH; Buffer[9] = AA55H; Buffer[10] = F00FH; Buffer[11] = 5AA5H; Buffer[12] = FF00H; /* * Memory is now set up. Let's point the SII initiator list * pointer to this structure. */ Shift Address of Buffer[0] right 2 places. Write this value into ILP. /* * Now that the SII is set up, let's define the data structures * that the microprocessor will need. Refer to the DSSI datalink * specification for further definition of these bytes. */ word CommandBytes[7]; word DataBytes[11]; /* * Now to begin the operation. We will set up some SII registers * correctly. The DICTRL,CSR and ID registers must be properly * initialized. */ /* * Put chip in loopback mode. */ DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-17 19 January 1987 Write 8 into the DICTRL register. /* * Enable selections and parity checking */ Write 6 into the CSR register. /* * Set up ID of the chip. */ Write 8007H into the ID register. /* * Note the ID register is set to 7. This is not a requirement. * However, if it is different, the command byte must be modified. * */ /* * Set up a pattern in the SDB register so that the SII thinks it * won arbitration. */ Write 80H into SDB register. /* * Let's enable DSSI mode in the SII. * The SII will attempt to select device 0. */ Write C0FFH into the DSCTRL register. /* SII is enabled */ /* * Note that all devices are DSSI devices. */ /* * Check SC1 until the SII asserts SEL. */ Read SC1 While (SC1 != 81H ) do Read SC1; /* * Now let's respond to the selection by asserting BSY and * set the phase to COMMAND OUT. */ DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-18 19 January 1987 Write 102H into SC1 /* * First the command bytes (Command phase) */ for (i=0,i<7,i++) do { CommandBytes[i]=GetCommByte(); Check that values are those expected. } /* * Now the data bytes (Data phase) * First, change phase to DATA OUT. */ Write 100H to SC1. for (i=0,i<0AH,i++) do { DataBytes[i]=GetDataByte(); Check that values are those expected. } /* * Now let's send the status (Status phase) * First set the phase to STATUS IN */ Write 103H to SC1. Set StatusByte to ACK (or NAK). SendStatusByte(StatusByte); /* * Disconnect from the bus. */ Write 0 into SC1. /* * Transfer is all over now. * Let's check the status in the buffer now. * The second word in the buffer should read 8000H */ Check that Buffer[1] is 8000H } } This procedure can be modified to verify the error-checking capabilities of the SII chip as an initiator. Several variations of this procedure will be enumerated and the differences in code included. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-19 19 January 1987 - Bad Status returned - Follow the above procedure, however return a value other than 61H. This includes simply changing the parity. Buffer[1] should read 8008H. - Phase Change at unexpected time - When acting as an initiator, the SII is capable of detecting unexpected changes and responding to them, as long as the change is one allowed by DSSI. Follow the above procedure except switch to status phase before the requested number of bytes have been delivered. Several cases may include 1. Switch to Status after 3 command bytes 2. Switch to Status after 6 command bytes 3. Switch to Status after 4 data bytes Buffer[1] should read 8004H. - Illegal Phase entered - The SII cannot handle phase changes to phases that are not allowed by DSSI. In this case, it will assert RST for 25 microseconds and abort the operation. Examples of illegal phases include: 1. Remain in COMMAND OUT for an eighth byte. 2. Remain in DATA OUT for an eleventh byte. 3. Enter an illegal phase (MESSAGE IN, DATA IN, etc.) and issue REQ. Buffer[1] should read 8014H. - Selection of non-DSSI device - The SII allows the programmer to place list elements destined for non-DSSI devices on the ILP list. The SII will arbitrate for the bus until it wins, and interrupt the processor with the BUF bit set. Follow the above procedure, except write C000H into the DSCTRL register. After arbitration, the SII should interrupt. Read the CSTAT to determine if this worked correctly. DSA in the DSCTRL register should also be deasserted now. - No element on ILP - In the process of adding an element to the ILP list, the SII may be inadvertently pointed to a 'done' buffer. This is fine because the SII will simply move onto the next buffer. However, if this was the last buffer, the SII has nothing to do. In this case, the SII will relinquish control of the bus (remember, the SII arbitrates and wins control of the bus before checking the list elements). Set up the memory as shown in the example, except make Buffer[1]=8000H. Allow the SII to win arbitration. However, the SII should never assert SEL, in fact it should drop BSY, as well. Check the ILP; it should read zero. DIAGNOSTIC ALGORITHMS - AN IMPLEMENTATION EXAMPLE Page B-20 19 January 1987 Whenever an initiator activity does not finish successfully, the OUTEN bit in the DSCTRL register will be deasserted. This should be checked following each of the error cases described above. APPENDIX C DATA LINK CODE - AN IMPLEMENTATION EXAMPLE C.1 INTRODUCTION SII Data Link code consists of two basic concepts; queuing output buffers and receiving input buffers. Other concepts include retries and reclaiming unused resources. These ideas will be discussed as they pertain to the SII. Again, these are only suggestions; implementations may choose other methods to implement these ideas. C.1.1 Adding An Element Onto The ILP In order to send a buffer to a remote node, the packet must contain correct header information and be placed on the list of outbound buffers. The following steps are needed to fill in the buffer header information: 1. Zero the buffer thread word - since this element is being added, it must be the last. 2. Zero the buffer status word - the status word must be cleared to allow the SII to process this buffer. 3. Fill in the ID of the remote device and interrupt enable bit in the buffer command word - bit 15 denotes whether the SII will interrupt upon completion of this buffer. Bits 2 through 0 denote the ID of the destination device. 4. Fill in entire buffer command field (six bytes) - these six bytes (command byte,flags byte, destination port, source port and length fields) must be written. 5. Link command bytes with data field - on output, the command bytes must be linked to the data field. Following the last command byte, the length of the data segment must appear. Bit 15 is set if there is a data segment following this one. The next word is the address of the data segment shifted 2 places to the right. DATA LINK CODE - AN IMPLEMENTATION EXAMPLE Page C-2 19 January 1987 6. Link together various data fields (if necessary) - if there are multiple data segments, these must also be linked together following the steps described above. Once the buffer is set up properly, it can be added to the list as follows: 1. Write the last item on the ILP list with the new buffer thread word, pointing to this new buffer. 2. If the ILP is zero, write it with the address of the new buffer. C.1.2 Retries This section only deals with setting up the SII to retry a buffer, it does not suggest a retry algorithm. When the SII attempts to send outbound traffic and is unsuccessful, it stops processing outbound data. Unsuccessful is defined as a packet which: 1. The target returned NAK 2. RST was asserted during the transfer 3. The target disconnected during the Status phase completed. 4. The target changed phase before the SII expected it would. Note that all these cases do not store a status of 8000H in memory. They either store a value other than 8000H or no status at all. Whenever the SII stops processing outbound traffic, one of the following situations has occurred: 1. the RST bit in CSTAT is set, generating an interrupt 2. the OBC bit in CSTAT is set, generating an interrupt 3. if the IE bit in the buffer was set, the LDN bit in CSTAT is set, generating an interrupt If the IE bit in the command word of each buffer is set, the SII is guaranteed to interrupt whenever it disables outbound traffic. DATA LINK CODE - AN IMPLEMENTATION EXAMPLE Page C-3 19 January 1987 The SII ILP will be pointing to the element which it had unsuccessfully attempted to deliver in all cases. Once the OUTEN bit in the DSCTRL register is set again, the SII will attempt to retransmit the failed buffer. C.1.3 Receipt Of Incoming Traffic Once the SII is in DSSI mode, it will continue to accept all incoming packets (as long as buffer space is available). The SII will interrupt on incoming traffic only if the IE bit in the buffer is set. Once a buffer is marked 'Done', the local intelligence is free to remove that buffer from the SII, and process it. C.1.4 Reclaiming Of Allocated Buffers Buffers that have not been marked 'Done' cannot be removed at will, since the current state of the SII with respect to that buffer is not known. For example, the processor may check the STLP and see that it points to the second buffer. It then decides to remove the fourth buffer. Between the time the TLP was read and the processor dequeued the fourth buffer, the SII could, theoretically have finished the second and third buffers and be using (or be ready to use) the fourth buffer. Removal of buffers (especially short buffers) once given to the SII is not recommended. If this must be done, the SII should be disabled from operating in DSSI mode. This is done as follows: 1. Clear the SLE bit in the CSR register. This disables the SII from responding to selection attempts. 2. Clear the OUTEN bit in the DSCTRL register. This disables the SII from sending any other buffers out. 3. The SII may be already busy processing a buffer (input or output) when the above steps were executed. Therefore the code must wait for the SII to be idle. The SII is idle when the MCDIAG register reads 100H. 4. Dequeue any buffers. APPENDIX D APPLICATION CIRCUITS D.1 ARBITRATING MODE The logic necessary to connect the SII, in arbitrating mode, to memory is small. The design has been done so as to allow implementations to use the SII with minimal support logic in this mode. This mode is most useful in allowing two devices (one of which is the SII) to access a shared memory. Most logic needed for arbitration is contained inside the SII chip. The following are the blocks needed to design this type of system. o Memory - this is the shared buffer memory to be used by the two devices. It is recommended that this memory be capable of faster than 200 ns cycles (150 ns is probably preferable). The address lines are called RAM_ADDR, while the data bus is HP_DAL. Control lines to the memories can be multiplexed using the HP_ BUSGRANT signal. o SII Address Counters - the SII does not issue an address cycle for each memory access that it does. Consequently, an external counter must be incorporated into the design. The SII provides a LOAD and CLOCK signal to be used by such a counter. The input to these counters is HP_DAL while the outputs are called SII_ADDR. o Ram Multiplexers - these multiplexers are needed to select either the SII ram address or device ram address for use with the memory. The inputs to these muxes should be DEV_ADDR and SII_ADDR. The output, RAM_ADDR is selected by the SII output, HP_BUSGRANT. A multiplexer is also needed to select the HP_WRITE signal or DEV_WRITE signal. A multiplexer is also needed to select either HP_DS or DEV_RAMCS to become the RAM_CS signal. The select for these is also HP_BUSGRANT. o Register Address Buffer - a single buffer, enabled by HP_ADREN, should be used to supply the register address and read/write line to the SII. The inputs to this buffer should be DEV_ADDR and DEV_WRITE. The outputs are APPLICATION CIRCUITS Page D-2 19 January 1987 HP_DAL<5:1> and HP_WRITE. o Data Transceivers - a set of transceivers, enabled by HP_DATAEN or HP_BUSGRANT, whose direction is selected by DEV_WRITE should be used to buffer the HP_DAL bus from the DEV_DATA bus. These transceivers are used to: 1. gate the SII register write data onto the HP_DAL lines. 2. gate the SII register read data onto the DEV_DATA lines. 3. gate the device ram write data onto the HP_DAL lines. 4. gate the device ram read data onto the DEV_DATA lines. The A input to these buffers is DEV_DATA, while the B input is HP_DAL. o Control Machine - control must be added to handle SII register cycles and device ram accesses. Outputs that must be generated by this block include: 1. HP_BUSREQ - a request for use of the SII bus 2. HP_CS - a request to access a SII register 3. DEV_RAMCS - a ram chip select used when the device accesses the memory. This completes the list of blocks needed to design an arbitrated memory using the SII chip. Again, this is a suggested implementation; designers may choose other methods of implementation. D.2 NORMAL MODE Normal mode of the SII requires more logic to interface to a system. This mode is used when the memory is multi-ported and the SII may be held off from accessing it. This mode allows the implementor to design his own arbitration scheme, rather than using that built into the SII. The basic design is similar to that presented in the previous example, with several exceptions. These differences will be enumerated below. o SII Data Buffers (or FIFO) - to allow the SII to operate at its peak rate, it is advisable that data to and from the SII be buffered. In this way, memory accesses are not limited to those times when the SII is accessing memory. APPLICATION CIRCUITS Page D-3 19 January 1987 o Control Machine - the control for this system is different from that described above. This machine must arbitrate the memory, generate RAM timing signals, return HP_RDY to the SII and perform SII register accesses. o Data Path - the data bus used for memory is isolated from the HP_DAL lines. The SII Data Buffers and Device Data Transceivers are used to separate the RAM_DATA bus from the HP_DAL bus and DEV_DATA bus, respectively.