
                   NS486SXF Boiler Plate Software - README                        
                   ---------------------------------------
 
                                    v1.6

                              November 26, 1996

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INTRODUCTION
------------

The "boiler plate" is a simple assembly program that can be loaded into 
the NS486 eval board flash with the Flash Loader utility. 

It performs NS486SXF setup similar to what most protected mode programs 
would do.  After that, it jumps to a label called "user_start", in
a second assembly file, "int.asm". 

The code in "int.asm" initializes the UART, displays a 'r',
and then loops displaying "123*".  The '2' character is printed by
an Interrupt Service Routine (called with an INT 20h instruction),
which demonstrates that the IDT table is function and shows how to
use the boiler plate macro to modify an IDT entry.

This is not intended to be a useful base for software development, but
an example that incorporates the following:
  
  initializing the DRAM, chip selects, cache
  setting up protected mode tables (GDT, IDT)
  demonstrating use of interrupts

CHANGES FROM v1.5
-----------------

  The BIU_RBATR register was changed from 0x7A to 0x5A.  Functionally, these
  are identical, as bits 6 and 5 are used to set the number of RDY extension
  periods, and values 10b and 11b in these registers both result in 2 RDY
  extensions.  However, the November 1996 Datasheet erroneously reports the 11b
  setting in these bits as three RDY extensions.

  The BIU_CSATR1 register was changed from 0xCA (from 0xBA).  The newest rev of
  the Altera FPGA for the evaluation board does not use the RDY signal to
  extend accesses to the external UART.  The previous versions did use the
  RDY signal for both external UART accesses and all IO accesses to PCMCIA
  cards.  This was undesirable so was removed.  This change required that the
  timing for the external UART be set correctly as no external logic lengthens
  the cycle.

CHANGES FROM v1.4
-----------------

Only a few things were changed from version 1.4:

  o Logical chip select 1 was changed to the range 0xFFF0_0000 to
    0xFFFF_FFFF.  This is the range allocated for flash on the evaluation
    board.  The actual flash device on the evaluation board starts at
    address 0xFFFC_0000.  Therefore, the 256K flash will be "shadowed"
    in the address space from 0xFFF0_0000 to 0xFFFB_FFFF.  However,
    setting up the chip select in the manner makes it easier to change
    ROM/Flash sizes without changing software.  The old version set the
    range from 0xFF80_0000 to 0xFFFF_FFFF, which greater than the range
    specified in the evaluation board documentation.
    
  o The BIU_RBATR register was changed from 0x1A to 0x7A.  This sets 2
    periods of RDY extension, which is closer to the ISA spec. and
    required for some ISA and PC/104 cards.
    
  o The BIU_CSATR1 register was changed from 0xAC to 0xBA.  The old value
    was incorrect, as it setup timing for logical chip select 1 that was
    different than that in BIU_RBATR.  Since logical chip select 1 is used in
    this code to extend the flash range, the timing should be the same as
    that set in BIU_RBATR.  Also, the timing for the external UART was
    changed to meet spec.
    
  o The bootup code in "boiler.asm" now jumps to an external label that is
    in the file "int.asm".  Previously the jump was to an absolute address,
    and two separate binaries had to be programmed into the flash.  Now
    the two assembly files are assembled and linked into one binary.
    
  o The code that sets up the chip select base and address range registers
    now uses 32 bit IO macros.  This is more readable.  The NS486SXF will
    break 32 bit IO accesses into 16 or 8 bit accesses as necessary.
    
  o Tons of documentation was added to the code.

DOCUMENTATION
-------------

Please see the source files for detailed documentation and to see how to
use this stuff.  

FILES
-----

These are the files:

        o boiler.asm   - main program
        o int.asm      - example test program

        o boiler.inc   - macros/equates for tests
        o io.inc       - macros for doing IO instructions
        o ns486reg.inc - equates for all NS486sxf registers
        o x86.inc      - macros for x86 instructions
        o uart.inc     - macros to do simple debug character output

        o makefile     - makefile to make the images

        o boiler.flc   - Flash Loader script to program the boiler
                         and INT test into flash

COMPILING
---------

The included makefile can be used to compile the images.  This makefile
can be modified if new tests are created.  This software compiles under
MASM 6.10.  The makefile works with Microsoft "nmake".

You can rebuilt the images from the source code by typing "nmake all".

You need the following tools: ml (MASM), link, exe2bin.  The linker (link)
should be an OMF version of link such as the one included with
Microsoft Visual C++ 1.5 or earlier.  Link and exe2bin were at one time
included with MS-DOS.

NOTE ON IMAGES
--------------

The way I set up this code, the two files generate an absolute
binary image (COM file).  This image must be located in ROM at a
specific area.

This method produces code that can simply be loaded on the evaluation
board and executed, without using any special embedded tools.

It would not be easy to integrate a C test program with the boiler
plate without using am embedded linker and locator.  The "NSDEMO"
code included with the evaluation board is much better suited for use
with high level languages.

RUNNING THE DEMO TEST
---------------------

The "readme.txt" file in the "FLASHLDR\" directory describes the use of the
Flash Loader and initial board setup and testing.  This Boiler Plate
program is used in a very similar manner to the hello program in the
Flash Loader directory.  

  load the flash loader utility and connect to the evaluation board
  the monitor jumper (W6) should be on and the board freshly reset
  ( FLASH CMD: conn )

  program this boiler plate and INT test into the flash
  ( FLASH CMD: boiler )  -- this runs the boiler.flc script

  go to terminal mode
  Hello World runs at 9600 bps, so the vtbaud variable should be at 9600
  ( FLASH CMD: vt )

  remove monitor jumper, reset board, and observe the character 'r' 
  followed by a repeating "123*"

  replace the monitor jumper, reset the board.  you should see the target
  loader sign-on message and repeating A's.

  Hit escape to exit terminal mode, and exit the flash loader utility
  ( FLASH CMD: exit )

The program can also be booted directly from the Flash Loader without
removing the jumper by typing the command:  boot boiler; vt

ENVIRONMENT
-----------

The environment is set up by boiler.asm as follows:
   
        GDT at 00A0000 to 00AFFFF
              several entries pre set up, see boiler.asm
        IDT at 00B0000 to 00B07FF
              all entries point to 08:00E0000
        Stack Segments allocated at:
              00C0000 to 00CFFFF - ring 0
              00D0000 to 00DFFFF - ring 3
        All data segment registers set to 10h
        Code segment register set to 08h
        Stack Segment set to 48h, ESP to FFFCh

A macro is provided to set up an IDT entry.  This is required to make a
interrupt jump somewhere other than 08:00E0000.  See "int.asm" for an
example of using interrupts.

Other useful macros are provided in the other include files.

UART
----

Macros are provided to initialize a debug UART and print a single
character.  This allows the user to see what parts of code are run or
in what sequence.

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