SECTION 3 TABLES


3 Reference Information

The following tables document a number of the hardware and software 
features of the AMSTRAD PC1512 some of which may have been already  
mentioned in earlier sections but are repeated here for easy reference.

3.1 Language Links.

The lower three bits of the Printer Status Channel (I/O address 379) are 
wired to reflect the (one's complement) state of a set of option links 
(LK1-LK3) located on the left side of the main board about 2 inches 
below the printer connector. They are used by the ROS firmware to define 
the language option or diagnostic mode option as detailed below.

     Link Value         ROS Usage
   
           0            English Language.
           1            German Language.
           2            French Language.
           3            Spanish Language.
           4            Danish Language.
           5            Swedish Language.
           6            Italian Language.
           7            Diagnostic Mode.

The ROS messages are displayed in the selected language. In diagnostic 
mode, the messages revert to English, and the normal testing is skipped. 
Any self test failures are reported but are ignored and upon completion 
a disk bootstrap is attempted. This enables loading of an extended set 
of diagnostic software.

3.2 Processor Memory Usage

The following is a repeat of the processor's physical memory layout in 
tabular form with interrupts and ROS areas included.

  Locations           Usage

00000-003FF           Processor interrupt vectors 0 to 255. To derive an 
                      individual interrupt vector's starting address multiply
                      the vector number by four.
                      
00400-00500           ROS Variables. (See section 2.4)
                      
00501-7FFFF           System (or User) RAM area. The 512K byte area 
                      (inclusive of the previous entries) is the normal
                      complement of system memory installed.

80000-9FFFF           128K Byte area where additional memory may be installed
                      in external 32K byte increments.

A0000-BFFFF           128K byte area reserved for 8-bit controller 
                      memory. The standard VDU screen memory resides in 
                      the address range from B8000 to BBFFF. Individual 
                      peripheral cards may make use of the other addresses
                      as the designer sees fit. For additional details,
                      consult the manual supplied with the card or its
                      manufacturer's agent.

C0000-EFFFF           192K byte area reserved for the expansion ROM's of 
                      the various peripheral cards. The optional Hard 
                      Disk controller uses the address range from C8000 
                      to CBFFF. 

F0000-FFFFF           64K byte area reserved for System ROM. The ROS 
                      resides in the 16K byte area from FC000 to FFFF. 
                      The remaining 48K bytes is reserved for future 
                      expansion. Address block occurs repeat from 16K 
                      byte ROS area occurs in this range.
                      
           
3.3 Keyboard and Key Codes.

    Key Code    Hex      (UK) Key Cap
    
       1         01           ESC
       2         02         1 and !
       3         03         2 and "
       4         04         3 and 
       5         05         4 and $
       6         06         5 and %
       7         07         6 and ^
       8         08         7 and &
       9         09         8 and *
       10        0A         9 and (
       11        0B         0 and )
       12        0C         - and _
       13        0D         = and +
       14        0E         <-DEL
       15        0F           TAB
       16        10            Q
       17        11            W
       18        12            E
       19        13            R
       20        14            T
       21        15            Y
       22        16            U
       23        17            I
       24        18            O
       25        19            P
       26        1A         [ and {
       27        1B         ] and }
       28        1C           CR<-
       29        1D          CTRL
       30        1E            A
       31        1F            S
       32        20            D
       33        21            F
       34        22            G
       35        23            H
       36        24            J
       37        25            K
       38        26            L
       39        27         ; and :
       40        28         ' and @
       41        29         # and ~
       42        2A       LEFT SHIFT
       43        2B         \ and |
       44        2C            Z
       45        2D            X
       46        2E            C
       47        2F            V
       48        30            B
       49        31            N
       50        32            M
       51        33         , and <
       52        34         . and >
       53        35         / and ?
       54        36       RIGHT SHIFT
       55        37       * and PrtSc
       56        38           ALT
       57        39         SPACE
       58        3A       CAPS LOCK
       59        3B           F1
       60        3C           F2
       61        3D           F3
       62        3E           F4
       63        3F           F5
       64        40           F6
       65        41           F7
       66        42           F8
       67        43           F9
       68        44           F10
       69        45        NUM LOCK
       70        46      SCROLL LOCK
       71        47       KEY PAD 7
       72        48       KEY PAD 8
       73        49       KEY PAD 9
       74        4A       KEY PAD -
       75        4B       KEY PAD 4
       76        4C       KEY PAD 5
       77        4D       KEY PAD 6
       78        4E       KEY PAD +
       79        4F       KEY PAD 1
       80        50       KEY PAD 2
       81        51       KEY PAD 3
       82        52       KEY PAD 0
       83        53       KEY PAD .
     84-111    54-6F      UNDEFINED
       112       70         DEL->
     113-115   71-73      UNDEFINED
       116       74         ENTER
     117-118   75-76      UNDEFINED
       119       77       JOY FIRE 2
       120       78       JOY FIRE 1
       121       79       JOY RIGHT
       122       7A       JOY LEFT
       123       7B       JOY DOWN
       124       7C       JOY UP
       125       7D       MOUSE M2
       126       7E       MOUSE M1
       127       7F       UNDEFINED

3.4 Asynchronous Communications Element (8250) Registers.

For serious design purposes, it is recommended that the designer obtain the 
standard INS8250 data sheets. The following excerpt are the major software
accessible registers.

Modem Status Register (MSR)[R6] - I/O Address 3FEh.

   Bit(s)     Function
   
     7        Data carrier Detect (DCD).
     6        Ring Indicator (RI).
     5        Data Set Ready (DSR).
     4        Clear To Send (CTS).
     3        Delta Data Carrier Detect (DDCD).
     2        Trailing Edge Ring Indicator (TREI).
     1        Delta Data Set Ready (DDSR).
     0        Delta Clear To Send (DCTS).

Line Status Register (LSR) [R5] - I/O Address 3FDh.

   Bit(s)     Function
   
     7        Always Clear (0).
     6        Transmitter Shift Register Empty (TSRE).
     5        Transmitter Holding Register Empty (THRE).
     4        Break Interrupt (BI).
     3        Framing Error (FE).
     2        Parity Error (PE).
     1        Overrun Error (OE).
     0        Data Ready (DR).

Modem Control Register (MCR) [R4] - I/O Address 3FCh.

   Bit(s)     Function
   
     7        Always Clear (0).
     6        Always Clear (0).
     5        Always Clear (0).
     4        Loop (Diagnostic Mode).
     3        Out2 (looped to RI).
     2        Out1 (Looped to DCD).
     1        Request To Send (RTS) (Looped to DSR).
     0        Data Terminal Ready (DTR) (Looped to CTS).

Line Control Register (LCR) [R3] - I/O Address 3FBh.

   Bit(s)     Function
   
     7        Divisor Latch Access (DLAB) (Selects Regs 0 & 1).
     6        Set Break.
     5        Stick Parity (Holds parity as EPS not if PEN set).
     4        Even parity Select (EPS).
     3        Parity Enable (PEN).
     2        Number of Stop Bits (STB) (0 = 1 Stop Bit, 1 => 1).
     1        Word Length Select Bit 1 (WLSS1). (0-3 = 5-8 Bits)
     0        Word Length Select Bit 0 (WLSS0).

Interrupt Identification Register (IIR) [R2] - I/O Address 3FAh.

   Bit(s)     Function
   
     7        Always Clear (0).
     6        Always Clear (0).                 IID Int Type
     5        Always Clear (0).                 
     4        Always Clear (0).                 3 Rx Line Status
     3        Always Clear (0).                 2 RX Data Available
     2        Interrupt ID Bit 1 (IID1).        1 Tx Holding Register Empty
     1        Interrupt ID Bit 0 (IID0).        0 MODEM Status 
     0        Not Interrupt Pending.

Interrupt Enable Register (IER) [DLAB = 0:R1] - I/O Address 3F9h.

When the Divisor Access Latch Bit (Line Control Register bit 7: DLAB) is 
clear, inputting I/O address 3F9 reads the IER.

   Bit(s)     Function
   
     7        Always Clear (0).
     6        Always Clear (0).
     5        Always Clear (0).
     4        Always Clear (0).
     3        Modem Status (EDSSI).
     2        Receiver Line Status (ELSI).
     1        Transmitter Holding Register Empty (ETBEI).
     0        Received Data Available (ERBAI).

   Receive Buffer Register (RBR)
   Transmit holding Register (THR) [DLAB = 0:R0] - I/O Address 3F8h.

When the Divisor Access Latch Bit (Line Control Register bit 7: DLAB) is 
clear reading and writing I/O location 3F8 accesses the RBR/THR 
registers. An input from I/O address 3F8 reads the Receiver buffer 
Register (bits 0 to 7). Outputting to I/O address 3F8 writes the 
Transmitter Holding Register. 

Divisor Latches MS & LS (DLL & DLM) [R0 & R1 when DLAB Set].

When the Divisor Access Latch Bit (Line Control Register bit 7: DLAB) is 
set, then registers 0 & 1 are the (16-bit) Divisor Register. The least 
significant bits are written to by outputting to address 3F8 and the 
most significant bits are written to by an output to location 3F9. The 
divisors and their respective baud rates are as follows:

  Baud Rate      Divisor          R1 & R0 (hex)
  
      75            1536            06-00
     300            384             01-80
     600            192             00-C0
    1200            96              00-60
    2400            48              00-30
    4800            24              00-18
    9600            12              00-0C

3.5 High Performance Programmable DMA Controller (8237A-4) Registers.

The following are the major software accessible 8237A registers.

Command register - Write I/O Address 008.

   Bit(s)     Function (Action... {1/0})
   
     7        DACK sense active {hi/lo}
     6        DREQ sense active {hi/lo}
     5        {Extended/Late} write selection.
     4        {Rotating/Fixed} priority.
     3        {Compressed/Normal} timing.
     2        {Disable/Enable} Controller.
     1        {Enable/Disable} Channel address hold.
     0        {Enable/Disable} Memory-to-memory (not supported).

Status Register - Read I/O Address 008

   Bit(s)     Function
   
     7        Channel 3 Request.
     6        Channel 2 Request.
     5        Channel 1 Request.
     4        Channel 0 Request.
     3        Channel 3 has reached TC.
     2        Channel 2 has reached TC.
     1        Channel 1 has reached TC.
     0        Channel 0 has reached TC.

Mode Register - I/O Address 00B [WO].

   Bit(s)     Function 
   
     7        Mode Select Bit 1. (Modes: 0 = Demand, 1 = Single,
     6        Mode Select Bit 0.        2 = Block, 3 = Cascade)
     5        Address {decrement/increment} select.
     4        Autoinitialisation {enable/disable}.
     3        Transfer Type Bit 1. (Types: 0 = Verify, 1 = Write,
     2        Transfer Type Bit 0.      2 = Read, 3 = Illegal)
     1        Channel Select Bit 1. (Channels: 0-3 respectively)
     0        Channel Select Bit 0.


Request Register - I/O Address 009h [WO].

   Bit(s)     Function 
   
     7        Don't Care.
     6        Don't Care.
     5        Don't Care.
     4        Don't Care.
     3        Don't Care.
     2        Request Bit {Set/Reset}.
     1        Channel Select Bit 1. (Channels: 0-3 respectively)
     0        Channel Select Bit 0.

Mask Set/Reset Register - I/O Address 00A [WO]

   Bit(s)     Function 
   
     7        Don't Care.
     6        Don't Care.
     5        Don't Care.
     4        Don't Care.
     3        Don't Care.
     2        {Set/Reset} Mask Bit.
     1        Channel Select Bit 1. (Channels: 0-3 respectively)
     0        Channel Select Bit 0.

Mask Write register - I/O Address 00F [WO].

   Bit(s)     Function 
   
     7        Don't Care.
     6        Don't Care.
     5        Don't Care.
     4        Don't Care.
     3        {Set/Clear} Channel 3 Mask bit.
     2        {Set/Clear} Channel 2 Mask bit.
     1        {Set/Clear} Channel 1 Mask bit.
     0        {Set/Clear} Channel 0 Mask bit.

3.6 Programmable Interrupt Controller (8259A-2) Command Words.

   Bit(s)     Function 
   
     7        N/A
     6        N/A
     5        N/A
     4        Always Set (1).
     3        {Level/Edge} Trigger Mode.
     2        Call Address Interval of {4/8}.
     1        {Single/Cascade} Mode (Need ICW3 if Single Mode).
     0        ICW4 {Needed/Not Needed}.

Initialisation Command Word 2 (ICW2) - Write I/O Address 021h.

   Bit(s)     Function 
   
     7        Interrupt Type Bit 7 (T7).
     6        Interrupt Type Bit 6 (T6).
     5        Interrupt Type Bit 5 (T5).
     4        Interrupt Type Bit 4 (T4).
     3        Interrupt Type Bit 3 (T3).
     2        Not used.
     1        Not used.
     0        Not used.

This byte selects one of the interrupt service vector locations (in 
absolute locations 0 through 3FF) to be used when interrupting. Type 
bits 3-7 (asserted on the data bus during the INTA cycle) map to address 
bits 5-9 for interrupt vector selection. The lower three type bits are 
derived from the interrupt level.

Initialisation Command Word 3 (ICW3) - Write I/O Address 021.

This command word is not used since Single (ICW1 bit 1) is always true 
in the PC1512. When used, this command word specifies which IR has a 
slave in Master mode, or it a slave then bits 0 through 3 specify the 
slave ID number (0 to 7).

Initialisation Command Word 4 (ICW4) - Write I/O Address 021.
                
   Bit(s)     Function (Action... {1/0})
   
     7        Always clear (0).
     6        Always clear (0).
     5        Always clear (0).
     4        {Enable/Disable} Special Fully Nested Mode.
     3        Buffered Mode {On/Off}.
     2        {Master/Slave} Mode (Only valid in Buffered Mode).
     1        {Auto/Normal} EOI.
     0        Always set (1) - (8086/8088 Mode).

Operation Control Words

The operation control words select various 8259A modes operation.

Operation Control Word 1 (OCW1) - Write I/O Address 021.

   Bit(s)     Function (Action... {1/0})
   
     7        Interrupt Mask 7 {Set/Reset}.
     6        Interrupt Mask 6 {Set/Reset}.
     5        Interrupt Mask 5 {Set/Reset}.
     4        Interrupt Mask 4 {Set/Reset}.
     3        Interrupt Mask 3 {Set/Reset}.
     2        Interrupt Mask 2 {Set/Reset}.
     1        Interrupt Mask 1 {Set/Reset}.
     0        Interrupt Mask 0 {Set/Reset}.

The eight mask bits either mask (i.e. inhibit when M=1) or enable their 
respective channels.

Operation Control Word 2 (OCW2) - Write I/O Address 020.

   Bit(s)     Function 
   
     7        Rotate (R) Bit.
     6        Specify (SL) Bit.
     5        End of Interrupt (EOI) bit.
     4        Always zero.
     3        Always zero.
     2        Level bit 2 (L2).
     1        Level bit 1 (L1).
     0        Level bit 0 (L0).

The level bits are required when specific (SL) is set.
Operation Control Word 2 (OCW2) - Write I/O Address 020.

   Bit(s)     Function 
   
     7        Always zero.
     6        Enable Special Mask Mode (ESMM) bit.
     5        Special Mask Mode (SMM) {Set/Reset}.
     4        Always zero.
     3        Always set.
     2        {Enable/Disable} Poll Command.
     1        Read Register (RR) enable bit.
     0        Read {IS/IR} register on next - RD pulse (RIS).

The ESMM bit must be set for the SMM bit to have any effect. Similarly, 
the RR bit must be set for the RIS bit to have an effect.

3.7 Programmable Interval Timer (8253) Registers.

The 8253 PIT has four addressable elements, the three counters (0-2) 
which are read or written 8 bits at a time (on I/O addresses 40-42) and 
the Control Word register (write I/O address 043).

The Control word register is as follows:

   Bit(s)     Function 
  
     7        Select Counter bit 1 (SC1).
     6        Select Counter bit 0 (SC0).
     5        Read/Load bit 1 (RL1).
     4        Read/Load bit 0 (RL0).
     3        Mode bit 2 (M2).
     2        Mode bit 1 (M1).
     1        Mode bit 0 (M0).
     0        {Enable/Disable} Binary Coded Decimal (BCD) counter.

The SC bits select counters 0-2 and the 3 (both bits set) state is illegal.

The RL bits enable the counter's Read/Load operation as follows:

  0:    Counter Latching - Snapshot current counter (to a holding register)
        for next read operation.
  1:    Read/Load MS byte only.
  2:    Read/Load LS byte only.
  3:    Read/Load LS byte first then the MS byte.

The Mode bits select one of five valid modes (six & seven wrap around to
modes two and three). The modes are as follows:

  0:    Interrupt on Terminal count.
  1:    Programmable One-Shot.
  2:    Rate Generator.
  3:    Square Wave generator.
  4:    Software Triggered Strobe.
  5:    Hardware triggered Strobe.

3.8 Real Time Clock (HD146818) Registers

The HD146818 is a CMOS peripheral device which combines three unique 
features: a complete time of day clock with an alarm and one hundred 
year calendar, a programmable periodic interrupt and square-wave 
generator, and 50 bytes of low-power static RAM.

The figure below shows the address map of the HD146818. The memory 
consists of 50 bytes of general purpose RAM, 10 RAM bytes which normally 
contain the time, calendar, and alarm data, and four control and status 
bytes. All bytes are directly readable and writable by the processor 
except Registers C and D which are read only. Bit 7 of Register A and 
the seconds byte are also read only.
         
                0         Seconds         00
                1        Sec Alarm        01
                2         Minutes         02
                3        Min Alarm        03
                4          Hours          04
                5        Hour Alarm       05
                6       Day of Week       06
                7       Day of Month      07
                8          Month          08
                9          Year           09
                10      Register A        0A
                11      Register B        0B
                12      Register C        0C
                13      Register D        0D
         
                14                        0E
                           50          
                          Bytes        
                           User        
                           RAM         
                63                        3F
         

3.8.1 Time, Calendar and Alarm, Locations

The processor obtains the time and calendar information by reading the 
appropriate locations. The program may initialise the time, calendar, 
and alarm by writing these locations. The contents of the 10 time, 
calendar, and alarm bytes may either be binary or binary-code decimal 
(BCD).

                     Before initialising the internal registers the SET 
bit in Register B should be set to a "1" to prevent time/calendar 
updates from occurring. The program initialises the 10 locations in the 
selected format (binary or BCD), then indicates the format in the data 
mode (DM) bit of register B. All 10 locations must use the same data 
mode, either binary or BCD. The SET bit may now be cleared to allow 
updates. Once initialised the real-time clock makes all updates in the 
selected data mode. The data mode cannot be changed without 
reinitialising the 10 data bytes.

The table below shows the binary and BCD formats of the time, calendar 
and alarm locations.

   Address     Function         Range   Binary data Mode    BCD Data Mode
   
      0        Seconds          0-59       00h-3Bh           00h-59h
      1        Seconds Alarm    0-59       00h-3Bh           00h-59h
      2        Minutes          0-59       00h-3Bh           00h-59h
      3        Minutes Alarm    0-59       00h-3Bh           00h-59h
   
               Hours                       01h-0Ch (AM)      01h-12h (AM)
      4        12-Hour Mode     1-12       81h-8Ch (PM)      81h-92h (PM)
               
               24-Hour Mode     0-23       00h-17h           00h-23h
   
               Hours Alarm                 01h-0Ch (AM)      01h-12h (AM)
      5        12-Hour Mode     1-12       81h-8Ch (PM)      81h-92h (PM)
               
               24-Hour Mode     0-23       00h-17h           00h-23h
   
      6        Day of Week      1-7        01h-07h           01h-07h
      7        Day of Month     1-31       01h-1Fh           01h-31h
      8        Month            1-12       01h-0Ch           01h-12h
      9        Year             0-99       00h-63h           00h-99h
   

For the Day of the Week, Sunday = 1.

The 24/12 bit in register B establishes whether the hour locations 
represent 1-to12 or 0-to-23. The 24/12 bit cannot be changed without 
reinitialising the hour locations. When the 12-hour format is selected 
the high-order bit of the hours represents PM when it is a "1". The 
time, calendar, and alarm bytes are not always accessible by the 
processor. Once per second the 10 bytes are switched to the update logic 
to be advanced by one second and to check for an alarm condition. If any 
of the 10 locations are read at this time, the data outputs are 
undefined. The update-in-progress (UIP) bit in Register A may be used to 
determine if the update cycle is in progress or not. The UIP bit goes 
high once per second and the update cycle begins 244S before the 
time/calendar data will be changed.

3.8.2 RTC Register Locations

The HD 146818 has four registers which are accessible by the processor. 
The four registers are fully accessible during the update cycle.

The bit assignments for register A (address 0Ah) are as follows:

      Bit       Assignment
      
       7        Update in Progress (UIP)
       6        Divider Bit 2 (DV2)
       5        Divider Bit 1 (DV2)
       4        Divider Bit 0 (DV2)
       3        Rate Selection Bit 3 (RS3)
       2        Rate Selection Bit 2 (RS2)
       1        Rate Selection Bit 1 (RS1)
       0        Rate Selection Bit 0 (RS0)

The UIP bit indicates whether the 10 time, calendar, and alarm bytes are 
being updated or not as explained above.

The three Divider bits (DV2-DV0) are used to identify which of the three 
time base frequencies is in use or to reset the divider chain.

The four rate selection bits (RS3-RS0) select one of 15 taps on the 22-
stage divider chain, or disable the divider output. The tap selected may 
be used to generate an output on the square (SQW) pin and/or a periodic 
interrupt.

The bit assignments for register B (address 0Bh) is as follows:

      Bit       Assignment
      
       7        SET Bit
       6        Periodic Interrupt Enable (PIE) Bit
       5        Alarm Interrupt Enable (AIE) Bit
       4        Update-ended Interrupt Enable (UIE) Bit
       3        Square-Wave Enable (SQWE) Bit
       2        Data Mode (DM) Bit
       1        24/12 hour format Bit
       0        Daylight Savings Enable (DSE) Bit

When the SET bit is a "0" the update cycle functions normally by 
advancing the counts once per second. When the SET bit is written to a 
"1", any update cycle in progress is aborted and the processor may 
initialise the time and calendar locations without updates occurring. 
SET is a read/write bit which is not modified by RES or internal 
functions of the HD 146818.

The PIE bit is a read/write bit which allows the periodic-interrupt flag 
(PF) bit to cause the IRQ pin to be driven low. The program writes a "1" 
to the PIE bit in order to receive periodic interrupts at the rate 
specified by the RS3-RS0 bits in Register A. A "0" in PIE blocks IRQ 
from being generated, but the periodic flag (PF) bit still goes high at 
the periodic rate.

The AIE bit is a read/write bit which when set to "1" permits the alarm 
flag to assert IRQ. An alarm interrupt occurs for each second that the 
three time bytes equal the alarm bytes. When AIE is a "0" the AF bit 
does not initiate an IRQ. The RES pin clears AIE to "0". The internal 
functions do not affect the AIE bit.

The UIE bit is a read/write bit which enables the update-end flag (UF) 
bit to assert IRQ. The RES pin goes low or the SET bit going high 
clears the UIE bit.

When the SQWE bit is set to a "1" by the processor, a square-wave signal 
at the frequency specified by the rate selection bits (RS3 to RS0) 
appears on the SQW pin. When the SQWE bit is set to "0" the SQWE pin is 
held low. The SQWE bit is cleared by the RES pin. SQWE is a read/write 
bit.

The DM bit indicates whether the time and calendar updates are to use 
binary or BCD format. DM is a read/write bit and is not modified by RES 
or internal functions of the HD 146818. A "1" in DM signifies binary 
data and a "0" specifies BCD data mode.

The 24/12 control bit specifies the format of the hour bytes. A "1" 
specifies 24-hour mode and a "0" specifies 12-hour mode. It is a 
read/write bit and is not affected by RES or any Hd 146818 internal 
functions.

The DSE bit is a read/write bit which when set to "1" enables daylight 
savings mode. When enabled, two special updates take place. On the last 
Sunday in April the time increments from 1:59:59 to 3:00:00 AM. On the 
last Sunday in October when the time first reaches 1:59:59 AM it is 
decremented to 1:00:00 AM. DSE is not changed by RES or any internal 
operations.

The bit assignments for register C (address 0Ch) are as follows:

      Bit       Assignment
      
       7        Interrupt Request Flag (IRQF) Bit
       6        Periodic Interrupt Flag (PF) Bit
       5        Alarm Interrupt Flag (AF) Bit
       4        Update-Ended Interrupt Flag (UF) Bit
       3        0
       2        0
       1        0
       0        0

The C register is a read-only register and a program write has no effect 
on any of the bits.

The IRQF bit is set by the logical equation: 
                    IRQF = PF.PIE + AF.AIE + UF.UIE
Any time the IRQF bit is a "1" the IRQ pin is driven low. All flag bits 
in the C register are cleared after a program read or when the RES pin 
is low.

The PF pin is et to a "1" when a particular edge is detected in the 
selected tap of the divider chain as selected by the RS# to RS0 bits. 
The PF bit is set to a "1" independent of the state of the PIE bit.

The AF bit is set to a "1" when the current time matches the alarm time.

The UF bit is set after each update cycle.

The remaining bits (3 to 0) are always low.

The bit assignments for Register D (address 0Dh) area as follows:

      Bit       Assignment
      
       7        Valid RAM Time (VRT) Bit
       6        0
       5        0
       4        0
       3        0
       2        0
       1        0
       0        0

The VRT bit indicates that the contents of the RAM and time are valid. A 
"0" appears in the VRT bit when the power sense (PS) pin is low. The 
processor can set the VRT bit when the time and calendar are initialised 
to indicate that they are valid. The VRT bit is a read-only bit and is 
not modified by the RES pin. The VRT bit can only be set by reading the 
D register.

Bits 6 to 0 are unused and are always read as zeros.

3.9 Floppy Disk Controller (PD765A).

The PD765A Floppy Disk Controller (FDC) contains two registers which 
are accessible by the CPU; the Main Status Register (at I/O address 
03F4) and the Data Register (at I/O address 03F5) both of which are 8 
bits wide. The Status Register contains the status of the FDC and may be 
accessed at any time. The Data Register is actually made up of several 
registers in a stack and stores data, commands and Floppy Disk Drive 
(FDD) status information. Data is written into the data register in 
order to program a particular command. The data address is read in order 
to obtain the result after an operation. The Main Status register (I/O 
address 3F4h) may only be read and is used to facilitate the transfer of 
data between the CPU and the PD765A FDC.

There are 15 separate commands which the PD765A FDC can execute. Each 
of these commands require multiple bytes to specify the operation fully.
The result after execution of the command may also be a multi-byte 
transfer back to the processor. Because of this multi-byte interchange 
of information between the processor and the FDC, it is convenient to 
consider each command as consisting of three phases:

Command Phase:     The FDC accepts all information to perform a 
                   particular operation from the CPU. 

Execution Phase:   The FDC performs the operation.

Result Phase:      After completion of the operation, status and 
                   housekeeping information are made available to the 
                   CPU.
                   
The PD765A contains five status registers. The main status register 
mentioned earlier which may be read at any time and the four result 
phase status registers (ST0, ST1, ST2 and ST3) which are only made 
available during the Result Phase after completion of a command. The 
particular command which has been executed determines which status 
registers will be returned.

The Command bytes which are sent to the PD765A during the Command Phase 
must occur in the order shown in the command table. That is, the command 
code must be sent first followed by the other bytes in the prescribed 
sequence. No foreshortening of the Command Phase or the Result Phase is 
allowed. After the last byte of the data in the Command Phase is sent 
the Execution Phase automatically starts. In a similar fashion, when the 
last byte of data is read out in the Result phase, the command is 
automatically ended and the PD765A is ready for a new command.

It is important to note that during the Result phase all bytes shown in 
the Command table must be read. The Read Data command, for example has 
seven bytes listed in the result phase. All seven bytes must be read out 
else a new command will not be accepted.

The status registers are as follows:

Main Status Register

      Bit(s)     Assignment
      
       7         Request for Master (RQM).
       6         Data Input/Output (DIO).
       5         Execution Mode (EXM).
       4         FDC Busy (CB).
       3         FDD 3 Busy (D3B).
       2         FDD 2 Busy (D2B).
       1         FDD 1 Busy (D1B).
       0         FDD 0 Busy (D0B).

Status Register 0 (ST0)

      Bit(s)     Assignment
      
       7         Interrupt Code bit 1 (IC1).
       6         Interrupt Code bit 2 (IC2).
       5         Seek End (SE).
       4         Equipment Check (EC).
       3         Not Ready (NR).
       2         Head Address (HD).
       1         Unit Select 1 (US1).
       0         Unit Select 2 (US2).

Status Register 1 (ST1)

      Bit(s)     Assignment
      
       7         End of Cylinder (EN).
       6         Always zero.
       5         Data Error (DE).
       4         Over Run (OR).
       3         Always zero.
       2         No Data (ND).
       1         Not Writable (NW).
       0         Missing Address Mark (MA).

Status Register 2 (ST2)

      Bit(s)     Assignment
      
       7         Always zero.
       6         Control Mark (CM).
       5         Data Error in Data Field (DD).
       4         Wrong Cylinder (WC).
       3         Scan Equal Hit (SH).
       2         Scan Not Satisfied (SN).
       1         Bad Cylinder (BC).
       0         Missing Address Mark in Data Field (MD).

Status Register 3 (ST3)

      Bit(s)     Assignment
      
       7         Fault (FT).
       6         Write Protect (WP).
       5         Ready (RY).
       4         Track 0 (T0).
       3         Two Side (TS).
       2         Head Address (HD).
       1         Unit Select 1 (US1).
       0         Unit Select 0 (US0).

The Commands are as follows:

Read data

Command Phase: 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}.
       6         (FM) Select {MFM/FM} {Single/Double density} Mode
       5         (SK) Enable Skip deleted data address mark.
       4         0.
       3         0.
       2         1.
       1         1.
       0         0.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
      
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1)

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector to be read.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Gap 3 Length.
Byte 9: DTL - Data Length to be read.

During execution data is transferred between the FDD and the CPU memory.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head read.
Byte 6: Final Sector read.
Byte 7: Number of bytes read.

Read Track

Command Phase: 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         0.
       6         (FM) Select {MFM/FM} {Single/Double density} Mode
       5         (SK) Enable Skip deleted data address mark.
       4         0.
       3         0.
       2         0.
       1         1.
       0         0.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector to be read.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Gap 3 Length.
Byte 9: DTL - Data length to be read.

During execution data is transferred between the FDD and the CPU memory. 
The FDC reads all data fields from index hole in EOT.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head read.
Byte 6: Final Sector read.
Byte 7: Number of bytes read.

Read Deleted Data

Command Phase: 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}.
       6         (FM) Select {MFM/FM} {Single/Double density} Mode
       5         (SK) Enable Skip deleted data address mark.
       4         0.
       3         1.
       2         1.
       1         0.
       0         0.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector to be read.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Gap 3 Length.
Byte 9: DTL - Data length to be read.

During execution data is transferred between the FDD and the CPU memory. 

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head read.
Byte 6: Final Sector read.
Byte 7: Number of bytes read.

Read ID

Command Phase 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         0.
       6         (MF) Select {MFM/FM} {Single/Double density} Mode
       5         0.
       4         0.
       3         1.
       2         0.
       1         1.
       0         0.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

During execution the first correct ID information on the cylinder is 
stored in the Data Register.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST0 - Status register 2 (See ST2 table).
Byte 4: Cylinder.
Byte 5: Head.
Byte 6: Sector.
Byte 7: Number of bytes per sector.

Write Data

Command Phase 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}
       6         (MF) Select {MFM/FM} {Single/Double density} Mode
       5         0.
       4         0.
       3         0.
       2         1.
       1         0.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

During execution data is transferred between the CPU memory and the FDD.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head written.
Byte 6: Final Sector written.
Byte 7: Number of bytes written.

Write Deleted Data

Command Phase: 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}.
       6         (MF) Select {MFM/FM} {Single/Double density} Mode
       5         0.
       4         0.
       3         1.
       2         0.
       1         0.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Gap 3 Length.
Byte 9: DTL - Data length to be written.

During execution data is transferred between the CPU memory and the FDD. 

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head written.
Byte 6: Final Sector written.
Byte 7: Number of bytes written.

Format Track

Command Phase 6 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         0.
       6         (MF) Select {MFM/FM} {Single/Double density} Mode
       5         0.
       4         0.
       3         1.
       2         1.
       1         0.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Number of bytes per sector.
Byte 4: Number of sectors per track.
Byte 8: GPL - Gap 3 Length.
Byte 9: D - Filler Byte.

During execution the FDC writes address headers to the entire track.

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Cylinder number.
Byte 5: Head.
Byte 6: Sector.
Byte 7: Number of bytes per sector.

Scan Equal

Command Phase 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}
       6         (FM) Select {MFM/FM} {Single/Double density} Mode
       5         (SK) Enable Skip deleted data address mark.
       4         1.
       3         0.
       2         0.
       1         0.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Gap 3 Length.
Byte 9: STP - Step Factor: 1 = Contiguous, 2 = Alternate Sectors.

During execution data is transferred from the CPU memory and compared 
with the data from the FDD. 

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head compared
Byte 6: Final Sector compared.
Byte 7: Number of bytes compared.

Scan Low or Equal

Command Phase 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}
       6         (FM) Select {MFM/FM} {Single/Double density} Mode
       5         (SK) Enable Skip deleted data address mark.
       4         1.
       3         1.
       2         0.
       1         0.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector to be compared.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Length of Gap 3.
Byte 9: STP - Step Factor: 1 = Contiguous, 2 = Alternate Sectors.

During execution data from the CPU memory is compared with data from the 
FDD. 

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head compared
Byte 6: Final Sector compared.
Byte 7: Number of bytes compared.

Scan High or Equal

Command Phase 9 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         (MT) Multi-Track {Enable/Disable}
       6         (FM) Select {MFM/FM} {Single/Double density} Mode
       5         (SK) Enable Skip deleted data address mark.
       4         1.
       3         1.
       2         1.
       1         0.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         HD - Head Select (0 or 1).
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: Cylinder Number (0-76).
Byte 4: Head Number (as specified in the ID field).
Byte 5: Sector to be compared.
Byte 6: Number of bytes per sector.
Byte 7: EOT - Final sector number on track.
Byte 8: GPL - Length of Gap 3.
Byte 9: STP - Step Factor: 1 = Contiguous, 2 = Alternate Sectors.

During execution data from the CPU memory is compared with data from 
the FDD. 

The Result phase returns 7 bytes:

Byte 1: ST0 - Status register 0 (See ST0 table).
Byte 2: ST1 - Status register 1 (See ST1 table).
Byte 3: ST2 - Status register 2 (See ST2 table).
Byte 4: Final Cylinder number.
Byte 5: Final head compared
Byte 6: Final Sector compared.
Byte 7: Number of bytes compared.

Recalibrate

Command Phase 2 bytes.

Byte 1: Command Code.

      Bit(s)     Assignment
      
       7         0.
       6         0.
       5         0.
       4         0.
       3         0.
       2         1.
       1         1.
       0         1.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         0.
       1         US1.
       0         US0 - Unit Select (0 or 1).

During execution phase, the Head is retracted to Track zero.
No status is returned during the result phase.

Sense Interrupt Status

Command Phase: 1 byte.

Byte 1: Command Code = 08h

The Result phase returns two bytes.

Byte 1: ST0 - Status Register 0.
Byte 2: PCN - Present Cylinder Number.

Specify

Command Phase: 3 bytes

Byte 1: Command Code = 03h.

Byte 2: SRT/HUT - Step Rate Time (4 Ms bits - in 1 ms increments)/Head 
                  Unload Time (4 LS Bits - in 16 ms increments).

Byte 3: HLT/ND - Head Load Time (Bits 1 to 7 - in 2 ms increments)/Non 
                 DMA Mode (Bit 0) 

Seek

Command Phase 3 bytes.

Byte 1: Command Code = 0Fh.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         0.
       1         US1.
       0         US0 - Unit Select (0 or 1).

Byte 3: New Cylinder Number.

During execution phase, the Head is positioned to the specified Cylinder.
No status information is returned during the result phase.

Sense Drive Status

Command Phase 2 bytes.

Byte 1: Command Code = 04h.

Byte 2: Head and Unit select.

      Bit(s)     Assignment
     
      7-3        Don't Care.
       2         0.
       1         US1.
       0         US0 - Unit Select (0 or 1).

Result Phase: 1 byte.

Byte 1: ST3 - Status Register 3.

Invalid Opcodes

All command codes not listed are considered invalid. When an invalid 
code is encountered the FDC returns the ST0 register with the MS bit 
(Invalid Opcode bit) set.
 













 



