SECTION 2 - FIRMWARE

This section describes the AMSTRAD PC1512 Resident Operating System 
(ROS). It defines the interfaces to all the interrupt service routines 
provided by the AMSTRAD PC1512 ROS firmware (ROM) and all RAM locations 
used by the ROS.

The following copyright message is stored at the beginning of the ROS 
starting at location 0003 (relative to its origin):

(C) Copyright 1986 Amstrad Consumer Electronics plc

The ROS physically occupies the highest 16K bytes (in the address range
of FC000 to FFFFF)  in the 1 Mega Byte addressing range of the 8086-2 CPU
(See Figure 1.1). The total 64K byte address range from hexadecimal 
F0000 to FFFFF is reserved for system ROM and this contains the reset 
and initialisation address FFFF0. For this reason the system ROM always 
spans the highest locations and extends downward. Also address 
wraparound (block repeat) occurs in the 64K byte range. Note that all 
address constants in this document are in hexadecimal unless otherwise 
noted.

All calls to the ROS firmware should be made through the software 
interrupts disclosed in this manual. Application programs should not 
attempt to access the locations within the ROM area directly. AMSTRAD 
reserves the right to modify the coding within the Resident Operating 
System ROM as it sees fit.

The ROS provides a set of service routines which perform various I/O 
functions:

1. Power-Up Initialisation and Self Test.
2. Keyboard input.
3. VDU display of characters and pixels.
4. Character I/O to the printer and serial ports.
5. System clock and real time clock support.
6. Disk I/O including format,read and write.

To ensure hardware independence of application programs all I/O 
processes should be done using the ROS. This avoids possible problems 
due to any hardware modifications and/or enhancements.

Note that all ROS messages will be displayed in the language selected by 
the language links (see section 3.1).

2.1 Power-Up Initialisation and Self Test

The Power-Up Initialisation and Self Test function is entered at 
location FFFF0, the CPU reset entry point. This routine performs all 
necessary hardware initialisation and self tests, sets up the BIOS RAM 
variable area, initialises all the interrupt locations used by the ROS, 
initialises external ROMs then loads and runs the disk bootstrap.

The ROS does not use the SYSTEM RAM (user Ram Area) for stack or program 
variables until it has been successfully tested. If a RAM error is found 
an error message should be displayed correctly, assuming that there is 
no other fault that may result in incorrect operation of the CPU or VDU.

The Power-Up Initialisation and Self Test process is as follows:

1. Disable maskable and non-maskable interrupts.

2. Run the ROS self test which tests the following:

        Checksum of the ROS.
        All system RAM fitted.
        64k of VDU RAM.
        VDU controller status bits.
        8237 DMA controller.
        8253 Programmable Interval Timer.
        8255 Programmable Peripheral Interface.
        RTC counting.
        The system serial interface.
        The system printer interface.
        8259 programmable interrupt controller.
        Mouse X and Y counter registers.

After a system reset all the self tests except the RAM tests are rerun. 
If the three option links in the least significant part of the system 
printer status register are set to all ones then only the keyboard and 
disk tests are run.

Refer to section 2.3 for the individual power-up self test details.

3. Checksum the NVR.

If the checksum of the NVR is incorrect then it is loaded with its 
default values (See section 2.5).

4. Initialise the 8253 Programmable Interval Timer.

Set up counter 0 to interrupt every 54.9337 milliseconds. Set up 
counter 1 to generate an output signal with a period of 15.13 
microseconds. Disable counter 2.

5. Initialise the 8237 DMA controller.

Set up DMA channel 0 for memory refresh. Disable channel 1,2 and 3.

6. Initialise the 8259 Programmable Interrupt Controller.

Disable (mask) all interrupt levels. Note that levels 0,1 and 6 are 
enabled (unmasked) later.

7. Initialise the Write Status Registers.

Write Status-1 is initialised from a byte in the NVR defining the number 
of drives fitted and the default VDU mode. The ROS also sets or resets 
bit 1 in the status register depending on whether or not an 8087 NDP is 
installed. See section 1.8 for further System Status-1 information.

Write Status-2 is initialised according to the amount of memory 
installed. The ROS assumes a minimum of 512K bytes and that additional 
ram may be added in contiguous 32k byte increments up to a maximum of 
640K bytes. The additional memory is sized according to the following 
procedures. The segment address of each of the four 32K byte RAM blocks 
is written to the first two bytes of each respective block. The segments 
are then verified from low to high until a non matching address or the 
last block is encountered. The setting of the Write Status-2 register is 
according to the RAM0-RAM4 table in section 1.8.3.

8. Initialise the ROS variable area in system RAM.

The ROS uses variables in the address range of 00300 to 00500. Refer to 
section 2.4 (RAM Variables) for a complete description of these 
variables and their respective initialised values.

9. Initialise the first 32 Interrupt Vectors.

The first 32 interrupt vectors are set up to reference the ROS routines 
as listed below. Software interrupt routines which do not perform any 
function reference a dummy routine that simply does a return  from 
interrupt (IRET) instruction. Hardware service interrupts which do not 
perform any function reference a dummy (HWIRET) routine which issues a 
nonspecific end-of-interrupt to the 8259 interrupt controller and then 
executes an IRET instruction.
                                              
                                                   
  Interrupt        Purpose                           Type

      0            Divide by Zero                    Hardware (HWIRET)
      1            Single Step                       Hardware (HWIRET)
      2            Parity error routine (NMI)        Hardware
      3            Break                             Hardware (HWIRET)
      4            Overflow                          Hardware (HWIRET)
      5            Print Screen                      Software
      6            Mouse button control              Software
      7            Reserved                          Software (IRET)
      8            System Clock interrupt            Hardware
      9            Keyboard interrupt                Hardware
     10            RTC interrupt                     Hardware (HWIRET)
     11            COMMS                             Hardware (HWIRET)
     12            COMMS                             Hardware (HWIRET)
     13            Hard Disk                         Hardware (HWIRET)
     14            Floppy Disk interrupt routine     Hardware
     15            Printer interrupt                 Hardware (HWIRET)
     16            VDU I/O                           Software
     17            System Configuration              Software
     18            Memory Size                       Software
     19            Disk I/O                          Software
     20            Serial I/O                        Software
     21            Enhanced Function                 Software
     22            Keyboard I/O                      Software
     23            Printer I/O                       Software
     24            System Restart                    Software
     25            Disk Bootstrap                    Software
     26            System Clock and RTC I/O          Software
     27            Keyboard Break                    Software
     28            External Ticker interrupt         Software
     29            VDU initialisation parameter      Software
     30            Disk Parameter table              Software
     31            External VDU matrix table         Software
                                                   

The interfaces to the above routines are detailed in section 2.3.

10. Initialise and Test the Disk interface.

The initialise function of interrupt 19 is invoked followed by the disk 
test (See 2.2.14).

11. Keyboard Self Test.

The Keyboard microcontroller returns 0AAh upon successful completion of 
its power-up self test (See 2.2.15).

12. Initialise the VDU.

The initial VDU setting is done according to the Port-A value as 
described in section 1.8.2.

13. Initialise the 8259 Interrupt controller.

Enable the 8259 interrupt controller on levels 0 (8253 counter 0), 1 
(keyboard scan code receiver), and 6 (765 floppy disk controller). All 
other 8259 interrupt levels are masked.

14. Display the ROS sign-on message.

During power-up the ROS checksums the NVR. After the sign-on message has 
been displayed, the ROS outputs a warning message if the NVR sum was 
incorrect. In the case that the NVR is OK ( and last startup data are 
valid) the time and date of the last switch on are displayed.

15. Enable the NMI.

If a NMI occurs the default ROS interrupt handler displays a RAM parity 
error message and hangs the system. This condition can only be rectified 
by switching the machine off.

16. Initialise all external ROMs.

The ROS checks for external ROMs between addresses C0000 and F4000 in 
800h (2k) byte increments. An external ROM which conforms to the 
following specifications will be initialised by the ROS:

1. The first two bytes contain the hexadecimal value 55AA.
2. The next two bytes contain the size in 512 (1/2K) byte increments.
3. The next byte is the initialisation routine entry point.
4. The LS byte of the byte sum of the ROM is zero.

When a ROM conforming to this specification is located then the 
initialisation entry is called. If the sum test fails then an error 
message is displayed and initialisation is not called.

17. Floppy Disk Bootstrap.

The ROS attempts to load the bootstrap sector (from drive A, side 0, 
track 0, sector 1) into memory at 07C00h. If the bootstrap sector loads 
successfully it is given control (far jump to segment 0000 offset 7C00). 
If after 10 retrys the bootstrap sector cannot be loaded then the ROS 
displays a message prompting the user to insert a system disk into drive 
A and press a key. The ROS then waits for the key press and repeats the 
bootstrap procedure.

2.2 Power-UP Self Tests

On Power-Up or following a system reset, the ROS performs a series of 
self tests on the hardware to verify proper operation. When a test 
failure occurs, the ROS displays an error message on the VDU and the 
system is locked up. The keyboard interface is treated differently in 
that the ROS repeats keyboard self test until it is successful.

The ROS executes all self tests except when the option links (LK1-LK3) 
are set (See section 1.10.3), the ROS will only run the keyboard 
interface test and the disk test. If either of these two tests fail an 
error message is displayed but the error is ignored. This allows the 
system to be brought up for diagnostic testing.

When a soft reset (Control, Alt & Del) is issued the ROS performs all the 
self tests except the system RAM (User Area RAM) test and the VDU RAM 
test.

2.2.1 Test Procedure.

Upon completion of the VDU RAM and 6845 VDU Controller test the ROS 
displays a message ("Pleas wait") on the first line of the screen to 
indicate that self testing is in progress and as each successive self 
test is started a dot is displayed on the screen.

The tests are run in the following order:

        1. ROS checksum test.
        2. VDU RAM and VDU (6845) Controller test.
        3. Direct Memory Access (8237) Controller test.
        4. Programmable Interval timer (8253) test.
        5. Programmable Peripheral Interface (8255) test.
        6. Real Time Clock (HD 146818) test.
        7. Asynchronous Communication Element (8250) test.
        8. Parallel Printer Port test.
        9. Mouse X and Y count register test.
        10. System RAM test.
        11. Programmable Interrupt Controller (8259) test.
        12  Disk test.
        13. Keyboard Interface test.              

The ROS uses the stack during the Disk test, the Keyboard interface test 
and the Programmable Interrupt Controller test. All other self tests are 
executed without using either the stack or any RAM variables.

2.2.2 Test Methods.

Most of the device diagnostic tests consist of a Data Path test and a 
Waveform test as described below:

Data Path test.

        The data path test checks the read/write path between the CPU 
        and a particular device. A pattern is written to a device and 
        then read back to verify the integrity of the data path. The 
        patterns are as follows:

        All zeros.
        All ones.
        Sliding single bit and complement across 8 bits.

Waveform test.

        The waveform test detects address decoding errors in a hardware 
        device. The waveform test consists of selecting a specific 
        address in a device, writing a test pattern (usually 0FFFFh) and 
        verifying that the same pattern can be read back. The waveform 
        test is done in both ascending sequential order (upwards) and 
        descending sequential order (downwards) in order to check that 
        the address decoding logic works correctly.

2.2.3 ROS Checksum Test.

All bytes in the Resident Operating System ROM are summed and then 
checked that the least significant byte of the sum is zero. If the check 
fails then an error message indicating faulty ROM checksum is displayed.

2.2.4 VDU RAM and VDU Controller test.

The following tests are performed to test the VDU RAM and the VDU 
controller:

        Data path test on the first byte of the four planes in the VDU 
        RAM.

        Upwards/Downwards waveform test on every location in the VDU 
        RAM.

        6845 VDU status register toggle bit test. This test confirms 
        that the toggle bit in the VDU status register reverses states 
        after each read of the status register.
        
        6845 VDU status register frame flyback timing test. This test 
        checks that the duration of the frame flyback signal conforms to 
        the specification.

        If any of the tests fail the faulty VDU error message is 
        displayed.

2.2.5 Direct Memory Access Controller test.

The upwards/downwards waveform test is used to confirm that the 
registers in the DMA controller chip can be addressed. Any failure will 
cause the faulty DMA error message to be displayed.

2.2.6 Programmable Interval Timer test.

The first 8253 test is a write/read data path test to counter 2 followed 
by a check that counter 1 counts at the correct rate. If either test 
fails an interval timer error message is displayed.

2.2.7 Programmable Peripheral Interface test.

The 8255 PPI tests consist of a data path test on each of the two system 
status channels (Status-1 and Status-2). The 8253 PIT OUT2 (Status-2) 
bit is also checked for proper operation. If either test fails the 
faulty real time clock error message is displayed.

2.2.8 Real Time Clock test.

The RTC seconds counter is tested to be counting at the correct rate. 
Next a data path test on the checksum byte of the NVR is run (and the 
checksum byte is restored). If either test fails the faulty real time 
clock error message is displayed. 

2.2.9 Asynchronous Communications Element test.

This test confirms that the transmitter and receiver of the 8250 (i.e. 
the system serial port) are functioning correctly (at least in 
diagnostic mode).

The 8250 is configured in loop mode, 9600 baud, 8 data bits, 1 stop bit 
and no parity. Two test patterns are transmitted and the received 
patterns are checked. The status register is monitored for no parity, 
framing or overrun errors. If either received pattern does not equal the 
sent pattern or an error is set in the status register the faulty system 
serial port error message is displayed.

2.2.10 Printer Parallel Port test.

A data path test is performed on the printer data latch. If any 
incorrect test pattern is returned, the faulty printer port error 
message is displayed.

2.2.11 Mouse X and Y Count Register test.

The X and Y registers are cleared and then read to verify that they both 
contain zero. If the test fails the faulty mouse coordinate register 
error message is displayed.

2.2.12 System RAM test.

The amount of System (User Area) RAM is determined using the procedure 
described in section 2.1. The data path test is run on all available RAM 
followed by an upwards/downwards waveform test. If either test fails the 
faulty RAM error message is displayed.

2.2.13 Programmable Interrupt Controller test.

The 8259 tests consist of a data path test on the interrupt mask 
register and an interrupt acknowledge test to confirm that interrupts 
can occur and be serviced. If the test fails the faulty interrupt 
controller message is displayed.

2.2.14 Disk test.

The disk test attempts to establish whether the drives fitted to the 
system seek correctly. The test moves the read/write heads to track 10 
on each drive. The ROS does not verify that the correct track was 
obtained. If any errors are reported than the floppy disk controller 
error message is displayed.

2.2.15 Keyboard Interface test.

Upon power-up or reset, the keyboard self test is performed by the 
keyboard controller firmware. The keyboard returns keycode 0AAh to 
signify the successful completion of its testing. If any key code other 
than 0AAh is returned the keyboard error message is displayed and 
keyboard reset is issued (which reruns the keyboard self test). The 
Keyboard test is repeated until the keyboard test passes. When test pass 
is received, the error message is removed from the screen and the test 
is exited as normal. During the keyboard test a short beep is sounded 
every five seconds to indicate that the test is in progress.


