1.11 Alpha/Graphics Colour VDU Controller

The VDU controller is implemented as a partially emulated MC6845 CRTC and 
provides either a colour alphanumeric display (Alpha) or a colour pixel 
display (Graphics). The frame rate is 60 Hz non-interlaced and 200 scan 
lines are displayed between the top and the bottom boarders. The highest 
resolution on a scan line between the left and right boarders is 640 pixels 
displayed.

The 16K Byte VDU screen memory area (from B8000 to BBFFF) is overlaid (in 
Graphics modes) in four planes giving a resultant 64K Bytes of display RAM 
and enabling sixteen colours to be available.

The sixteen colours available on the display are as follows:

 Red    Green  Blue  Intensity  Luminance    Colour

  0      0      0       0           0        Black
  0      0      1       0           1        Blue
  0      1      0       0           4        Green
  0      1      1       0           5        Cyan
  1      0      0       0           2        Red
  1      0      1       0           3        Magenta
  1      1      0       0           6        Brown
  1      1      1       0           7        White
  0      0      0       1           8        Grey
  0      0      1       1           9        Light Blue
  0      1      0       1           12       Light Green
  0      1      1       1           13       Light Cyan
  1      0      0       1           10       Light Red
  1      0      1       1           11       Light Magenta
  1      1      0       1           14       Yellow
  1      1      1       1           15       Intense White
                                          

The "Light" colours imply higher intensity video.

On the monochrome monitor the R, G, B and I signals are summed and weighted 
2, 4, 1 and 8 respectively to form the 16 level grey scale luminance column 
in the table.

1.11.1 Alpha Display

Two Alpha modes are available: either (medium resolution) 40 characters by 
25 rows or (high resolution) 80 characters by 25 rows. The modes require 
2000 bytes or 4000 bytes of display RAM respectively. A low resolution 160 
by 100 pixels 16 colour graphics mode may be obtained in high resolution 
Alpha mode by programming the CRTC for two scan lines per character, and by 
using certain half-block characters in the character set as pixels. This 
mode requires 16000 bytes of display RAM.

The character set is formed by a ROM character generator and each of the 
256 characters is made up of a 8 by 8 pixel matrix. Each character 
displayed takes up two bytes of display RAM consisting of a character 
code byte and an associated attribute byte. The attribute byte allows a 
choice of either 16 foreground and 8 background colours per character, plus 
blinking, or a choice of 16 colours for both foreground and background 
without blinking. The display border may be any one of the 16 colours.

The display starting address in the display RAM is programmed via the CRTC. 
The starting address must be an even address boundary and it addresses the 
first (leftmost) character position in the top row of the display. In each 
pair of display RAM bytes, The even address is for the character code and 
the odd address is for the attribute byte. Subsequent characters are 
displayed along the row from left to right. When the end of a row is 
reached the next pair in the display RAM appears in the first character 
position of the next row down.

The attribute byte for each is as follows:

   Bit(ATn)        Definition

       7           Intensity (Background) or enable Blink
                      (Depends on Mode Control Bit 5)
       6           Red (Background)
       5           Green (Background)
       4           Blue (Background)
       3           Intensity (Foreground)
       2           Red (Foreground)
       1           Green (Foreground)
       0           Blue (Foreground)
              

There are two Graphics modes available either Mode 1 (medium resolution) 
320 pixels per scan line with a choice of four colours per pixel or Mode 2 
(high resolution) 640 pixels per scan line with a choice of sixteen colours 
per pixel. The modes require 16000 and 64000 bytes of display RAM 
respectively.

The display RAM is divided into four 16K byte planes one each for all the 
Red, Green, Blue and Intensity bits. Each plane may be individually written 
or read by the CPU, and two or more planes may be selected by the CPU for 
writing simultaneously with the same data.

1.11.2.1 Graphics Mode 1

The colour planes are not used in Mode 1, since only 16K bytes of display 
RAM (i.e. one plane) is ever required. For this reason system reset or 
entry into any other display mode than graphics mode2 forces selection of 
all planes for simultaneous writing by the CPU, which appears (to the 
software) as though only one 16K byte display RAM is installed in the 
address range from B8000 to BBFFF.

In Mode 1, the display memory for one scan line (320 pixels) consists of 80 
bytes. Each pixel requires two bits such that four pixels are specified by 
each byte. The leftmost pixel is contained in the two MS bits of the byte 
and the two bit pairs for the remaining pixels follow on logically in left 
to right fashion. The two bit field for each pixel specifies one of four 
colours in one of three palettes (See 1.11.3 - VDU Control Registers). The 
three palettes are as follows:

  B1    B0     Palette 0      Palette 1      Palette 2     

  0     0      Background     Background     Background
  0     1      Green          Cyan           Cyan
  1     0      Red            Magenta        Red
  1     1      Yellow         White          White
                                          

In Mode 1 the 100 even scan lines (0,2,4,...198) are contained in the 
graphics memory space from B8000 to B9F3F and the 100 odd scan lines 
(1,3,5,...199) are contained in the memory address range from BA00 to 
BBF3F. The graphics memory appears as follows:


                 <--320 Pixels (2 Bits Per)-->   

  B8000          Scan Line 0 (80 Bytes)             B804F
  B8050          Scan Line 2                        B809F
  B80A0          Scan Line 4                        B80EF
  B80F0          Scan Line 6                        B813F
  B8140          Scan Line 8                        B818F
    .                 .                               .
    .                 .                               .
  B9EF0          Scan Line 198                      B9F3F 
 
  BA000          Scan Line 1                        BA04F
  BA050          Scan Line 3                        BA09F
  BA0A0          Scan Line 5                        BA0EF
  BA0F0          Scan Line 7                        BA13F
    .                 .                               .
    .                 .                               .
  BBEF0          Scan Line 199                      BBF3F
                                                 

The layout of a byte of graphics RAM in Mode 1 is as follows:

              Ĵ
  RAM Bit:      7:6    5:4    3:2    1.0  
  Pixel:         0      1      2      3   
  Pixel Bit:   B1:B0  B1:B0  B1:B0  B1:B0 
              Ĵ

1.11.2.2 Graphics Mode 2

In Mode 2 the four memory planes become active and the colour of each pixel 
is controlled by the setting of the VDU Colour Plane Write Register at the 
time a pixel is written. The display memory for one scan line consists of 80 
bytes, each containing 8 pixels. Since there are four planes, each displayed 
pixel is actually made up from 4 bits of information (R, G, B, I) specifying 
one of 16 colours. The border is programmable to any one of the 16 colours.
The ROS emulates two colour 640 by 200 graphics mode (software mode 6) by 
writing to all four colour planes (intense White). Then the VDU Colour Plane 
Select register is used as the foreground palette selector. See section 
2.3.7.

The layout of a byte of graphics RAM in Mode 2 is as follows:

             Ŀ
  RAM Bit:    7  6  5  4  3  2  1  0 
             Ĵ
  Pixel:      0  1  2  3  4  5  6  7 
             

The address mapping of the scan lines in display RAM for mode 2 is identical 
to that depicted for display Mode 1 - all even scan lines (from B8000 to 
B9F3F) followed by all odd scan lines (from BA000 to BBF3F). The major 
difference is that data written to one location may actually be stored in up 
to four planes simultaneously.

Note that even though the same physical address range is used between 
graphics and text modes, the internal data storage within VDU RAM changes 
between the different modes. This means that data patterns stored in 
successive locations in text modes will be found in the IRGB planes when 
graphics mode 2 is selected. Also data patterns stored in graphics mode 1 
will be found on all planes when graphics mode 2 is selected. It is 
therefore not generally an accepted practice to store information in one VDU 
mode and then switch to another mode else unexpected results may be 
encountered.

1.11.3 VDU Control Registers

There are five programmable registers for VDU mode and colour selection. 
These consist of the VDU Mode Control Register, the VDU Colour Select 
Register, the VDU Colour Plane Write Register, the VDU Colour Plane Read 
Register, and the VDU Graphics Mode 2 Border Register.

On power-up or following a system reset, the control registers are preset as 
described below.

1.11.3.1 VDU MODE Control Register

The VDU MODE Control Register is a write only register located at I/O 
address 3D8. It is used to control the state of the VDU circuitry, selecting 
Alpha or Graphics mode and the various sub options available within Alpha 
and Graphics modes.
The layout of the VDU Mode control register is as follows:


   Bit        Output Use

    7         No Effect
    6         No Effect
    5         Enable Blinking Characters (disable intensified backgrounds)
    4         Select Graphics Mode 2 (de-select graphics mode 1)
    3         Enable Video Display
    2         Select Palette 2 (de-select palettes 0,1)
    1         Select Graphics modes (de-select Alpha modes)
    0         Select Alpha 80 Character mode (de-select 40 Character mode)
         

When bit 5 is set in Alpha modes, the foreground of all displayed characters 
with attribute bit 7 (AT7) set will blink at 1.875 Hz (1/32 frame rate) in 
synchronism with frame flyback. Bit 5 has no effect in Graphics modes.

Bit 4 (Select Graphics Mode 2) has no effect in Alpha modes.

In Alpha modes, clearing bit 3 forces the display, except the border, to 
black. In Graphics modes, the display is forced to the current border 
colour.

The Select Palette 2 bit (bit 2) has no effect in Alpha modes or in Graphics 
mode 2. It is used in conjunction with bit 5 of the VDU colour select 
register to control graphics mode 1 palette. To select palette 2, bit 5 of 
the VDU colour select register must be reset and bit 2 of the VDU mode 
control register must be set.

Bit 0 (Select Alpha 80 Char mode) has no effect in Graphics modes.

To avoid unsightly effects on the screen, this register should be updated 
during frame flyback time. Any kind of mode changing should preferably be 
done with the video disabled. Mode changing involves the use of bits 1 and 0 
and usually some re-programming of the CRTC.

On power-up and following a system reset, all bits of this register are 
cleared to zero.

1.11.3.2 VDU Colour Select Register

The VDU Colour Select Register is a write only register located at I/O 
address 3D9 and is used for controlling border colour in alpha modes and for 
selecting palette, border and pixel colour options in the graphics modes. 
The layout of the VDU Colour select register is as follows :

 Bit   Alpha Modes        Graphics Mode 1           Graphics Mode 2

 7,6   No Effect          No Effect                 No Effect
  5    No Effect          Select Palette 1          No Effect
                           (De-select palette 0) 
  4    No Effect          Foreground Intensity      No Effect
                           for palettes 0,1 & 2  
  3    Intensity          Intensity (Background     Intensity (Pixel)
        (Border)           and Border)           
  2    Red (Border)       Red (Background           Red (Pixel)
                           and Border)           
  1    Green (Border)     Green (Background         Green (Pixel)
                           and Border)           
  0    Blue (Border)      Blue (Background          Blue (Pixel)
                           and Border)           
                                                 

In Graphics mode 2, the display border colour is programmed via the VDU 
Graphics Mode 2 Border register. The ROS makes use of the VDU Colour Select 
register in VDU I/O software mode 6 as a palette selector by writing all 
graphics in bright white. The overall screen palette is then controlled by 
setting the VDU Select register (which is initialised to 07h by the ROS on 
selection of mode 6). This mode effectively emulates 2 colour 640 by 200 
graphics mode using 16K Bytes of VDU memory. (See section 2.3.7 - VDU I/O.)

When using the full 16 colour capability in Graphics Mode 2, programmers 
must set the VDU Colour select register to 0Fh and vary the plane selection 
with the Colour Plane Write Register.

To avoid unsightly effects on the screen this register should only be 
updated during frame flyback time.

On power-up or following a system reset, all bits in this register are 
cleared.

1.11.3.3 VDU Colour Plane Write Register

The VDU Colour Plane Write Register is a write only register located at I/O 
address 3DD. It is used in Graphics Mode 2 for controlling which colour 
plane or combination of colour planes will be written to when addressing the 
display RAM (B8000 to BBFFF hex).

The bit assignments for the VDU Colour Plane Write register are as 
follows:

   Bit        Output Use

   7-4        No effect
    3         Allow CPU write to Intensity Plane.
    2         Allow CPU write to RED Plane.
    1         Allow CPU write to Green Plane.
    0         Allow CPU write to Blue Plane.
         

The CPU simultaneously writes the memory planes that are enabled for writing.

Writing to this register has no effect except in Graphics Mode 2.

Following the selection of Graphics Mode 2, (other than when already in 
Graphics Mode 2) bits 0 through 3 are set to one, but may subsequently be 
changed by writing to this channel.

1.11.3.4 VDU Colour Plane Read Register 

The VDU Colour Plane Read Register is a write only register located at I/O 
address 3DE. It is used in Graphics Mode 2 for controlling the selection of 
which one of the four colour planes in the display RAM is to be read by the 
CPU when memory in the 16K byte address range from B8000 to BBFFF (hex) is 
read. The bit assignments for the VDU Colour Plane Read register are as 
follows:

   Bit        Output Use

  7-2         No effect 
   1          Read Select bit 1 (RDSEL1) 
   0          Read Select bit 0 (RDSEL0) 
         

The CPU reads from whichever one of the four colour planes in display RAM is 
selected according to the RDSEL value as follows:

   Bit        Colour Plane Selected for CPU read

    0         Blue Plane
    1         Green Plane
    2         Red Plane
    3         Intensity Plane
         

Writing to this register has no effect except in Graphics Mode 2.

On power-up or following a system reset or selection of any other mode than 
Graphics Mode 2 the register is cleared and fixed so that the CPU will only 
read from the Blue Plane.

1.11.3.5 VDU Graphics Mode 2 Border Register

The VDU Graphics Mode 2 Border Register is a write only register located at 
I/O address 3DF. It is used in Graphics Mode2 for specifying the border 
colour.

The bit assignments for the VDU Graphics Mode 2 Border register are as 
follows:

   Bit        Output Use

   7-4        No effect
    3         Border Intensity
    2         Border Red
    1         Border Green
    0         Border Blue
         

Bits 0 through 3 specify one of sixteen colours.

To avoid unsightly effects on the screen this register should only be 
updated during frame flyback time.

On power-up or following a system reset, or following selection of Graphics 
Mode 2 (other than when already inn Graphics Mode 2) the register is cleared 
(Graphics Mode 2 border black).

1.11.4 VDU Status Register

The VDU Status Register is a read only register located at I/O address 3DA. 
It may be read at any time to determine the following:

   Bit        Input Use

   7-4        Undefined
    3         Frame Flyback Time
    2         Light-pen switch off
    1         Light-pen latch set
    0         Toggle bit
         

Frame flyback time starts at the same time as the bottom border and lasts 
for 46 horizontal scan periods, ending 16 scans before the end of the 
subsequent top border.

Bit 2 reflects the state of the light-pen push button switch, which is 
neither latched nor debounced.

Bit 1 when set (1) indicates that the light pen latch is set, triggered 
either by a pulse from the light pen or by writing data to set the light pen 
channel. Writing any data to the Clear Light Pen channel clears the latch, 
which is undefined following power-up and unaffected by system reset.

When the VDU Status Register is read bit 0 toggles to the opposite state. 
Bit 0 is cleared (0) following power-up or following system reset.

1.11.5 MC6845 CRTC Emulation

The VDU controller is a partial emulation of a MC6845 CRT Controller device. 
Some of the registers which are programmable in an actual MC6845 are not 
programmable in the AMSTRAD PC1512. These differences are noted in the table 
which follows.

The remaining registers must be programmed according to the VDU mode of 
operation required in conjunction with the VDU Mode and Colour Select 
Registers previously described. A mode changing operation should be 
performed in the following sequence: Disable video, reprogram the CRTC as 
required, reprogram the Mode and Colour select registers as required, 
(maintaining video disabled), initialise display RAM as required, enable 
video.

The CRTC is controlled by way of two I/O addresses, the CRTC Address
register and the CRTC Data I/O location. The CRTC Address register is a 
write only register located at I/O address 3D0 (and all even addresses to 
3D6). The address register is a 5 bit register used to select one of the 
eighteen internal control registers (r0-R17). Addresses greater than 17 
produce no results. Once the CRTC Address register has been loaded, the CRTC 
Data I/I location which is located at I/I 3D1 (and all od addresses to 3D7) 
allows access to the selected internal CRTC register. Depending on the 
particular register selected the location may be either Read/Write (RW), 
Read Only (RO) or Write Only (WO).

The emulated MC6845 CRTC internal register layout and their initialised 
values are as follows:


Register   Register Name          Alpha 40   Alpha 80   Graphics    R/W
 Number                           Char Mode  Char Mode    Modes     Type

   R0     *Horizontal Total         --         --          --         -
   R1      Horizontal Displayed    [40]       [80]        [40]       WO
   R2     *Horizontal Sync Posn.    --         --          --         -
   R3     *Horizontal Sync Width    --         --          --         -
   R4     *Vertical Total           --         --          --         -
   R5     *Vertical Total Adj.      --         --          --         -
   R6     *Vertical Displayed      [25]       [25]       [100]       WO
   R7     *Vertical Sync Posn.      --         --          --         -
   R8     *Interlace                --         --          --         -
   R9      Max Raster Address       07         07          01        WO
   R10     Cursor Start Raster      06         06          06        WO
   R11     Cursor End Raster        07         07          07        WO
   R12     Start Address (MS)       00         00          00        WO
   R13     Start Address (LS)       00         00          00        WO
   R14     Cursor Location (MS)     00         00          00        RW
   R15     Cursor Location (LS)     00         00          00        RW
   R16     Light Pen Posn. (MS)     -          -           -         RO
   R17     Light Pen Posn. (LS)     -          -           -         RO
                                                                  

Note that all values are in decimal format.

Registers marked '*' are not software programmable in the emulated MC6895 
CRTC implementation, unlike a real MC6895. They are fixed in hardware 
according to the VDU mode currently selected.

The two sets of register values marked '[]' should normally be programmed 
non-zero. The magnitude of the non-zero value will have no effect on the 
display, but a zero value in either register will cause the whole of the 
screen to display the border colour.

The cursor function of a 6845 CRTC is supported only in Alpha modes. The 
cursor blinking function is performed by a circuit external to the CRTC and 
blinks the cursor at 3.75Hz (1/16 frame rate) in synchronism with frame 
flyback. The cursor non-display feature, variable blink rate feature and 
variable blink period feature of the 6845 CRTC are not supported.

The valid range of values for Cursor Start Raster (R10) is from 0 to 30 
(decimal) and the value of 31 (which will turn the cursor off). Values 
greater than 31 are not recommended.

The light pen function of a 6845 CRTC is supported:

                        Horizontal Resolution     Vertical Resolution

Alpha Modes:            1 Character Column        1 Character Row
Graphics Modes:         1 Pixel Word              2 Scans (i.e. 1 row)

If "M" = Current Display Address then in ...

Graphics, LPEN value = M + 1 or M + 2.
Alpha 80, LPEN value = M + 3 or M + 4.
Alpha 40, LPEN value = M + 1 or M + 2.

1.11.6 CRTC Display Addressing

In Alpha modes, the CRTC register values for start address and light pen 
position are in the 8K range 0000h to 1FFFFh, and wraparound occurs above 
this range. The register value corresponding to a character position in 
display RAM must be derived from the even byte address in the 16K range 
B8000h to BBFFFh by subtracting B8000 and halving.

In Graphics modes, the CRTC register values for start address and light pen 
position are in the 4K range 000h to FFFh and wraparound occurs above this 
range. A register value corresponds to two pairs of pixel bytes in display 
RAM on word boundaries, one pair displayed on an even scan and the other 
pair displayed on the following odd scan in the same horizontal position.

The register corresponding to the pixel, byte pair position in display RAM 
must be derived from the even byte address in the 8K range B*000h to B9FFFh 
(for a even scan) by subtracting the address offset B8000h and halving. 
Similarly for the odd scan line the offset BA000h is subtracted from an even 
byte address in the range BA000h to BBFFFh and halved.

1.11.6.1 Mode Mapping Relationships

There are important differences in the way the VDU Controller maps and uses 
the display RAM for different VDU display modes.

The Alpha Mode to Graphics Mode memory mapping follows the scheme depicted 
in fig 1.3.

The concept of planes does not exist in character mode and character data is 
stored sequentially is display RAM. In Graphics modes, the display RAM is 
viewed logically as colour planes which are grouped in four byte groups. 
This means that there is an effective "gear change" between alpha and 
graphics modes and storing in an address such as B8000h in graphics modes 
spans the address range from B8000 to B8003 in alpha modes.

In Graphics Mode 1, the display RAM mapping is the same as for Graphics Mode 
2, but only the data contained on the Blue plane is used to form pixels on 
the screen. When the CPU writes to display RAM in Graphics Mode 1, the same 
data is stored in all planes.

It is very important to note that it is impossible to store character and 
attribute pairs in consecutive display RAM in graphics mode. Attempting to 
clear the text screen with text data while in graphics mode and then 
switching to an alpha display mode will produce a "Stars and Bars" effect on 
the screen.

1.11.6.2 Display RAM Access Overhead

The VDU display timing and system CPU/DMA timing are derived from different, 
unrelated reference frequencies. For this reason CPU accesses to the display 
RAM must be synchronised to the display timing by the VDU controller, and 
this is done by inserting CPU wait states as appropriate.

Whenever the CPU accesses the display RAM, the total number of 125nS wait 
states incurred, including those already added automatically by the 8bit bus 
conversion process, will range from a minimum of 12 to a maximum of 46. At 
most, a situation in which 46 wait states are necessary could incur once 
every 63.77S, in all modes. Similarly, the need for 38 wait states could 
occur at most every 63.7S in Graphics mode 2 or in 80 x 25 Alpha mode.

                            Display RAM Mapping
                                  Fig 1.3
Ŀ
Disp.                                                                
RAM      0      1      2      3      4      5      6      7     ---  
Byte                                                                 
Ĵ
Alpha  B8000  B8001  B8002  B8002  B8002  B8002  B8002  B8002  B8xxx 
Modes Char. 0Attr. 0Char. 1Attr. 1Char. 2Attr. 2Char. 3Attr. 3Char./ 
                                                              Attrib.
Ĵ
Graph.B8000 IB8000 RB8000 GB8000 BB8001 IB8001 RB8001 GB8001 BB8xxx  
Mode  Pixel- Pixel- Pixel- Pixel- Pixel- Pixel- Pixel- Pixel- 4 Byte 
 2    Byte 0 Byte 0 Byte 0 Byte 0 Byte 0 Byte 0 Byte 0 Byte 0 Pixel  
      for Intfor Redfor Grnfor Blufor Intfor Redfor Grnfor BluGroups 
      Pix 0-7Pix 0-7Pix 0-7Pix 0-7Pix8-15Pix8-15Pix8-15Pix8-15       
Ĵ
Graph.                     B8000                       B8001         
Mode     X      X      X   Pixel     X      X      X   Pixel         
 1                         Byte 0                      Byte 1        
                           Pix 0-3                     Pix 4-7       

                                                                    
                              
                                                                    
                P0    P1    P2    P3          P4    P5    P6    P7  
               Ĵ       Ĵ
               B1B0B1B0B1B0B1B0       B1B0B1B0B1B0B1B0
                      

                   B1/B0 Selects colour with palette - see 1.11.2.1

                  X   Ignored on read, copy of "Blue" plane on write.

1.11.6.3 Alpha Mode Character Generator ROM

The 8K Character generator ROM can contain a maximum of four different 
character sets, each in a different 2K byte quadrant of the ROM. Only one 
character set can be used at a time and it is selected by means of two 
option links, LK6 and LK7, located on the right hand side of the main board.

The character set selection is as follows:


   LK7     LK6     Character Set Selected

                
   Out     Out     ROM Fourth Quadrant - Default factory setting.
   In      Out     ROM Third Quadrant - (optional Danish).
   Out     In      ROM Second Quadrant - (optional Danish).
   In      In      ROM First Quadrant - (optional Greek - late models).
                

1.12 Floppy Disk Controller

The floppy disk controller is based on the NEC PD765A single chip 
controller, and supports one or two 5.25 inch single or double sided, MFM 
double density floppy disk drives with a data rate of 250 kilobits per 
second.

The FDC is controlled by way of a Drive Selection register (at I/O Address 
3F2) and it is defined as follows:

   Bit(Dn)        Output Use             

    7-6           No effect.
     5            Switch motor(s) on and enable drive 1 selection.
     4            Switch motor(s) on and enable drive 0 selection.
     3            Allow 765A FDC to interrupt and request DMA
     2            765A reset
     1            Drive Select Bit 1 (DS1)
     0            Drive Select Bit 0 (DS0)
               

The Drive Select bits (DS1,DS0) are only valid for values of 00 and 01 for 
drives 0 and 1 respectively. The drive selection qualification is only 
completed when either bit 4 (for drive 0) or bit 5 (for drive 1) is set. In 
addition setting bits 4 or 5 will have no effect until the value of DS1, DS0 
is correspondingly set.

Bit 2 when cleared (0) holds the 765A reset until bit 2 is again set (1). 
Note that a reset must last for at least 3.5 S.

On power-up or following a system reset, all bits in this register are 
cleared to zero.

1.12.1 FDC Hardware Conditions

The hardware imposes the following conditions on the use of the 765A 
controller and disk drives:

1. The clock frequency of the 765A FDC is fixed at 4.0 MHz.

2. Disk data transfers are done by DMA using the on-board DMA controller. The 
   765A DRQ output may be connected to or disconnected from the DMA controller 
   DRQ2 input by software using Drive Selection Register bit 3.

3. An interrupt level is available for use by the 765A to signal command 
   completion and attention status to the CPU. The 765A INT output may be 
   connected to or disconnected from the interrupt controller IRQ6 input by 
   software using Drive Selection Register bit 3.

4. Drive 0 is always present. Drive 1 is optional. Drives 2 and 3 are not 
   implemented and can never be accessed. Drive Ready output signal from the 
   currently selected drive is connected to the 765A RDY input. For drives 
   which do not have a drive ready output the 765A RDY input may be 
   optionally fixed to the true condition.

5. The 765A Drive Select outputs US1 and US0 are not used to select the 
   drives This function together with motor control is done via the Drive 
   Selection Register which is external to the FDC 765A.

6. The FLT (Fault) input 765A is forced permanently false.

7. A Two-Sided status signal from the drive(s) is not provided but interface 
   to the drives allows the use of double sided drives.

8. Write precompensation of 250 nS is provided.

9. The 765A may be individually reset by software using Drive Selection 
   Register bit 2.

1.13 RS232C Asynchronous Serial Port

The asynchronous serial port is based on the National IN8250 ACE (or UART), 
single channel device.

The clock frequency input of the 8250 is 1.8432 MHz(0.1%).

The 8250 BAUD OUT output is connected to the RCLK input.

An interrupt level is available for use by the 8250. When the 8250 OUT2 
output is driven low (i.e. a 1 is written to bit 2 of the 8250 MODEM Control 
Register) then the INTRPT signal is connected to the interrupt controller 
IRQ4 input.

1.13.1 Serial Channel Interface

The serial interface uses a 25-way subminiature D type plug (male) connector 
emulating a DTE (Data Terminal Equipment).

The electrical levels of signal levels on this interface conform with EIA 
(Electronics Industry Association) standard RS-232C (and the equivalent 
CCITT V.24 interface standard).

The RS232C drivers and receivers between the 8250 and the serial channel 
connector are all inverting.

1.13.2 Serial Channel Pin Arrangement

 Pin     EIA     CCITT     Description     

   1     AA      101       Frame Ground
   2     BA      103       TxD - Serial Data Output
   3     BB      104       RxD - Serial Data Input
  *4     CA      105       RTS - Request to Send Output
   5     CB      106       CTS - Clear to Send Input
   6     CC      107       DSR - Data Set Ready Input
   7     AB      102       Signal Ground (Common Return)
   8     CF      109       DCD - Data Carrier Detect Input
  *20    CD      108.2     DTR - Data Terminal Ready Output
   22    DE      125       RI - Ring Indicator Input
                        

*  These interchange circuits, where implemented, shall be used to detect 
either a power off condition in the equipment across the interface, or the
disconnection of the interconnecting cable. The terminator for these 
circuits shall interpret the power off condition or the disconnection of the 
interconnecting cable as an OFF condition.


                 1  2  3  4  5  6  7  8  9 10 11 12 13 
              __________________________________________
              \  o  o  o  o  o  o  o  o  o  o  o  o  o /
               \                                      /
                \ o  o  o  o  o  o  o  o  o  o  o  o /
                 \__________________________________/

                 14 15 16 17 18 19 20 21 22 23 24 25

                 Viewed from the rear of the machine

See Appendix 3 for additional details of serial signals and cable 
connections.

1.14 Parallel Printer Interface

The parallel printer port is described in section 1.10 and is a general 
purpose 'centronics' style 8-bit interface. The printer interface uses a 25-
way subminiature 'D' socket (female) connector located at the back of the 
PC1512.

The Pin assignments for the printer connector is as follows:


   Pin       Assignment             

            ___________
    1       Data Strobe
    2       Data Bit 0
    3       Data Bit 1
    4       Data Bit 2
    5       Data Bit 3
    6       Data Bit 4
    7       Data Bit 5
    8       Data Bit 6
    9       Data Bit 7
            ___________________
    10      Printer Acknowledge
    11      Printer Busy
    12      Paper Out
    13      Select Printer        13 12 11 10  9  8  7  6  5  4  3  2  1  
            ________________    __________________________________________
    14      Select Auto Feed    \  o  o  o  o  o  o  o  o  o  o  o  o  o /
            _____________        \                                      / 
    15      Printer Error         \ o  o  o  o  o  o  o  o  o  o  o  o /  
            _____________          \__________________________________/   
    16      Reset Printer                                                 
            ________________       25 24 23 22 21 20 19 18 17 16 15 14    
    17      Printer Selected                                              
    18      GND                    Viewed from the rear of the machine    
    19      GND
    20      GND
    21      GND
    22      GND
    23      GND
    24      GND
    25      GND
          

Appendix 4 contains the Amstrad PL-2 printer specification for the DMP3000 
printer. 

1.15 Keyboard Interface

Keyboard data input to the CPU is via the 8255 PPI Port A, and the keyboard 
interrupt (level 1) of the 8259A PIC. Both of these have been previously 
described in sections 1.6 and 1.8.

1.15.1 Serial Clock and Serial Data

The Serial Clock and Serial Data signals are used for keyboard interface. 
These two bidirectional signals are used by the keyboard microcontroller to 
send keycodes to the main electronics board. The main electronics board also 
uses the same two signals to indicate readiness to receive another keycode 
back to the microcontroller. In addition these two signals are used to reset 
the microcontroller under hardware or software control.

1.15.2 Keyboard to main Board Interface

The quiescent state for both Serial Clock and Serial Data is high. A minimum 
of 5 S must separate a transition of one signal from another transition 
of the same signal, or any transition of the other signal.

Keycodes are sent from the keyboard microcontroller to the main board in 8-
bit serial form; MS bit first. Keycode data received by the main board is 
clocked into a shift register as either a "1" bit sequence or as a "0" bit 
sequence. To be interpreted as a "1" bit, the Serial Data signal must remain 
high during the time period when Serial Clock goes low and returns to the 
active high state. To be interpreted as a "0" bit, Serial Data must be low 
prior to the Serial Clock transition from high to low. Serial Data will then 
go high followed by Serial Clock. The "1" bit or the "0" bit is clocked into 
the shift register on the falling edge of the Serial Clock. 

1.15.3 Main Board to Keyboard Interface

Upon receiving a keycode from the microcontroller, within 5S of the last 
clock falling edge, the main board electronics drives the Serial Data line 
low and maintains it low until it is ready to receive a new keystroke. When 
the main board returns the Serial Data signal to the high state the 
microcontroller is free to send another keystroke. This response to the 
reception of a keycode is termed the ACKNOWLEDGE sequence.

The mainboard electronics causes a Reset to the keyboard microcontroller by 
driving the Serial Clock line low for 10 miliseconds or more. The state of 
the Serial Data signal does not affect the reset sequence.

1.15.4 Keycodes

The 8-bit keyboard data is capable of 128 make codes and correspondingly 128 
break codes. For any key which is pressed, the (make) keycode produced is in 
the range of 0-127 decimal. When a key is released, the (break) keycode 
produced is the same as the make code except that the top bit is set so that 
the value is in the range of 128-511 (decimal). The keycodes and their 
corresponding token values are covered in the ROS firmware (Section 2.3.5).

After a key is pressed and the keycode has been sent to the main board 
electronics, if no new keys are pressed and the key has remained pressed for 
more than one second, then the keyboard microcontroller re-sends the keycode 
every 83 milliseconds provide that the main board indicates by an 
Acknowledge sequence that it is ready to accept a new keycode.

The keycode AA hexadecimal is sent after a reset to indicate a successful 
completion of power-up tests.

1.15.5 Keyboard Connector

The Keyboard Connector is a 6-way Din socket. The pin assignment is as 
follows:

   Pin       Assignment          Viewed from the left hand side of the machine
                    _   _
    1        KBCLK                           5  /o_o\  1
    2        KBDATA                            /   6   \
    3        M1                             4   o o o   2
    4        GND                               \   o   /
    5        +5 Volts DC                         \ _ /
    6        M2                                    3
          

The M1 and M2 signals are connected directly from the mouse connector to be 
input to the keyboard controller in order to produce keycodes.

1.16 Mouse Interface

The Mouse Interface consists of two switch inputs from push buttons and two 
8-bit X & Y coordinate counters. The two mouse switches (M1 & M2) are 
arranged to form part of the keyboard matrix and are handled as keyboard 
data (producing low level keycodes 7E and 7D respectively).

The Mouse X-Coordinate at I/O Address 078 is an 8-bit counter which can be 
read by the CPU. Any write access regardless of the value written to the X-
Coordinate location clears the counter. Similarly the Mouse Y-Coordinate at 
I/O Address 07A can be read by the CPU or cleared by any write access to its 
I/O address.

The counters are incremented or decremented according to the direction of 
movement of the mouse, and their values indicate the mouse movement since 
last read or cleared. The X-Coordinate counter increments for "Right" motion 
and decrements for "Left" motion. The Y-Coordinate counter increments for 
"UP" motion and decrements for "Down" motion. In order to properly track 
mouse motion, software should read and clear the coordinate counters at a 
rate high enough to prevent overflow from positive values to negative values 
or negative values to positive values for a fairly high rate of mouse 
movement. The scaling of mouse movement is such that one increment of the 
counter represents 1/8 mm of physical mouse motion.

The delivered operating systems have AMSTRAD specific mouse drivers which 
actively perform the Read-and-Clear operation (every 18 ms) using the ticker 
interrupt.  This can cause the appearance of no mouse motion to the casual 
observer sampling the mouse coordinate counters. See Appendix 1 for 
additional details concerning Mouse Software Interfaces.

1.16.1 Mouse Connector

The mouse connector is a 9 way D type (female) connector located on the left 
hand side of the case and it has an AMSTRAD specific pinout. Attaching any 
other manufacturer's hardware (even though the connector may be similar) to 
the PC1512 mouse connector may cause serious damage to either the main board 
electronics or to the alternative (mouse) hardware.

The mouse connector pins are as follows:

   Pin       Assignment          
    
    1        XA
    2        XB
    3        YA
    4        YB
    5        Spare
    6        M1
    7        +5 Volts DC
    8        GROUND
    9        M2
          

The first four pins contain optically encoded phase XA, XB, YA and YB square 
waves. For positive motion the square wave on the A phase leads the B phase 
by 90 degrees with the reverse being true for negative motion. The remaining 
pins carry Mouse Button 1 (M1), 5V power, Ground, and Mouse Button 2 (M2) 
signals.

                  5  4  3  2  1
                _________________
                \ o  o  o  o  o /
                 \  o  o  o  o /
                  -------------
                    9  8  7  6

         Viewed from left hand side of machine

1.17 Joystick Interface

The AMSTRAD PC supports an industry standard joystick interface. The 
joystick inputs are handled as keycodes from the keyboard interface. The low 
level keycodes are in the range of 7C down to 77 (hexadecimal) corresponding 
to Up, Down, Left, Right, Fire1 and Fire2 respectively. The ROS firmware 
(See section 2) translates the directional codes to cursor key tokens and 
the Fire buttons can be assigned variable tokens depending on NVR settings. 
Please note that this is not an analogue interface. In order to use an 
analogue joystick an analogue card for the expansion slots is required.

1.17.1 Joystick Connector

The joystick connector is a 9 way D type (male) connector with an industry 
standard pinout. Attaching an incorrect device (even though the connector 
may be similar) to the PC1512 joystick connector may cause serious damage to 
either the main board electronics or to the incorrect (joystick) hardware.

The Joystick Socket is located on the rear left corner of the keyboard. Its 
pinout is as follows:

   Pin       Assignment          
    
    1        Up
    2        Down
    3        Left
    4        Right
    5        Spare
    6        Fire 2
    7        Fire 1
    8        Common
    9        Not Connected
          

                  1  2  3  4  5
                _________________
                \ o  o  o  o  o /
                 \  o  o  o  o /
                  -------------
                    6  7  8  9

           Viewed from rear of keyboard

1.18 Light Pen Connector

The AMSTRAD PC1512 Supports a standard light pen interface via the emulated 
MC6845. The Light Pen connector is located by removing the expansion slot 
cover at the top rear of the machine. The connector is located inside the PC 
case on the right hand edge of the main board just forward of the expansion 
card connectors. It consists of a 6-way berg strip and is labeled PL8 (LIGHT 
PEN) in large letters. Pin 1 is the forward most pin viewed from the front 
of the machine (the disk drive end).

The pin assignments are as follows:


   Pin       Assignment          
    
             _______________
    1        Light Pen Input
    2        (Keyway)
             ________________
    3        Light Pen Switch
    4        Ground
    5        +5 Volts DC
    6        +12 Volts DC
          

    Ŀ
                                                      ________________     
                                                     ________________    
                                                      ________________     
                                                     ________________    
                                                      ________________     
                                                     ________________    
    Ĵ
                                                 Light Pen Connector      
                  Ŀ    6       
                                                                5       
                                                                4       
                                                                3       
                                                                2       
                                                                1       
                                                                        
                                                                         
                                                                         


1.19 Expansion Interface

The AMSTRAD PC1512 has three slots for additional peripheral cards. These 
consist of a set of connectors on the rear right of the main board. The Pin 
numbering of each connector is the same and is such that the left (ground 
plane) side is numbered B1-B31 top to bottom and the right (component) side 
is numbered A1-A31 top to bottom. The following table defines the pin 
assignments of the expansion interface:


 Pin         Signal                      In/Out

 A01    Not I/O CHCK                     In
 A02    I/O Data Bit D7                  In/Out
 A03    I/O Data Bit D6                  In/Out
 A04    I/O Data Bit D5                  In/Out
 A05    I/O Data Bit D4                  In/Out
 A06    I/O Data Bit D3                  In/Out
 A07    I/O Data Bit D2                  In/Out
 A08    I/O Data Bit D1                  In/Out
 A09    I/O Data Bit D0                  In/Out
 A10    I/I RDY                          In
 A11    AEN - Address Enable             Out
 A12    I/O + Mem/Address Bit A19        Out
 A13    I/O + Mem/Address Bit A18        Out
 A14    I/O + Mem/Address Bit A17        Out
 A15    I/O + Mem/Address Bit A16        Out
 A16    I/O + Mem/Address Bit A15        Out
 A17    I/O + Mem/Address Bit A14        Out
 A18    I/O + Mem/Address Bit A13        Out
 A19    I/O + Mem/Address Bit A12        Out
 A20    I/O + Mem/Address Bit A11        Out
 A21    I/O + Mem/Address Bit A10        Out
 A22    I/O + Mem/Address Bit A09        Out
 A23    I/O + Mem/Address Bit A08        Out
 A24    I/O + Mem/Address Bit A07        Out
 A25    I/O + Mem/Address Bit A18        Out
 A26    I/O + Mem/Address Bit A18        Out
 A27    I/O + Mem/Address Bit A18        Out
 A28    I/O + Mem/Address Bit A18        Out
 A29    I/O + Mem/Address Bit A18        Out
 A30    I/O + Mem/Address Bit A18        Out
 A31    I/O + Mem/Address Bit A18        Out

 B01    Ground                           --
 B02    Reset                            Out
 B03    +5 Volts DC                      --
 B04    IRQ2                             In
 B05    -5 Volts DC                      --
 B06    DREQ2                            In
 B07    -12 Volts DC                     --
 B08    Not connected (Reserved)         In
 B09    +12 Volts DC                     --
 B10    Ground                           --
        __________________            
 B11    MEW (Memory Write)               Out
        _________________             
 B12    MRD (Memory Read)                Out
        _______________               
 B13    IOW (I/O Write)                  Out
        ______________                
 B14    IOR (I/O Read)                   Out
        _____                         
 B15    DACK3                            Out
 B16    DREQ3                            In
        _____                         
 B17    DACK1                            Out
 B18    DREQ1                            In
        _____                         
 B19    DACK0                            Out
 B20    CLK                              Out
 B21    IRQ7                             In
 B22    IRQ6                             In
 B23    IRQ5                             In
 B24    IRQ4                             In
 B25    IRQ3                             In
        _____                         
 B26    DACK2                            Out
 B27    T/C                              Out
 B28    ALE                              Out
 B29    +5 Volts DC                      --
 B30    CK14                             Out
 B31    Ground                           --
                                      


   31                                                                 1   B
  Ŀ
   Ŀ 
      
    Ŀ  
    
  
                                                                          A
                          Expansion Bus Connector
            Viewed from above while standing in front of machine

The I/O expansion slots are laid out the same as the industry standard 16-
bit Personal Computer Bus. The translation from the internal 16-bit 8086 bus 
to the 8 bit I/O bus layout is done by main board circuitry. Any 16-bit CPU 
I/O transfers will be broken down into two 8-bit cycles (with wait states) 
by this circuitry.

All signals are TTL compatible and can support a maximum loading of two low-
power schottky (LSTTL) loads per slot. Power supply loading per slot should 
be limited to a maximum of 900 milliamperes on the +5 Volt supply, to 33 
milliamperes on the -5 Volt supply, to 50 milliamperes on the +12 Volt supply 
and to 50 milliamperes on the -12 Volt supply. See Appendix 6.

Note that direct access to the on-board 16-bit fast memory bus is not 
available via the I/O expansion slots.

Additional engineering details for prototyping adapter boards should be 
supplied as part of the documentation for that particular hardware.

1.20 Video Connector

The video connector is a 8-way Din socket located in the rear of the 
computer. Its pinout is as follows:

   Pin       Assignment          
    
             ____________________
    1        Composite H & V sync
             _________
    2        Intensity
    3        GND                       6  __   __  7
    4        Black                       /  |_|   \
             _____                     /   o 8 o    \
    5        Green                  1   o   o   o    3
             ____                      \  o  o  o   /
    6        Blue                      4 \ ______ / 5
    7        GND                              
             ___                             2
    8        Red
                                         Video Plug
                                       (from monitor)

1.12 Power Connector

The power connector ia 14-way Din Socket located in the rear of the 
computer. Power is routed from the power supply located in the monitor to 
the main board electronics through the power connector. Its pinout is as 
follows:

   Pin     Assignment        MAX CURRENT

    1      Not Connected  
    2      0 Volts DC     
    3      +5 Volts DC       -(SEE NOTE 1)
    4      0 Volts DC     
    5      +5 Volts DC       -(SEE NOTE 1)           Power Plug
    6      Not Connected                           (from monitor)
    7      Not Connected                                               
    8      0 Volts DC                             10   __   __   11
    9      -12 Volts DC      0.24 AMP                 /  _  \
    10     0 Volts DC                           8   /  o     o  \    9
    11     +12 Volts DC      4.9 AMP              /  o  o   o  o  \
    12     0 Volts DC                         6     o 12 o 13 o     7
    13     -5 Volts DC       1 AMP                \   o  14   o   /
    14     Not Connected                         4  \  o  o  o  /  5
                                                      \ ______/
                                                      2           3
                                                            1


Note 1: Pins 3 and 5 are connected together to the +5 Volt bus for a total 
of 7.00 Amp maximum rating.

Note 2: See Appendix C for Power consumption data.

