AMSTRAD personal computer PC1512. AMSTRAD PC Technical Reference Manual
SOFT 50011

Preface
-------
This Technical Reference manual is intended primarily to assist writers 
of software for the Amstrad PC1512, although in conjunction with the 
PC1512 Service manual it will be of interest to designers of add-on 
hardware.

It is assumed that the reader has a working knowledge of the Industry 
Standard architecture comprising of an 8086 ( or 8088 ) with DMA, PIT, 
RTC and Interrupt Controller support chips; plus Colour Graphics Adapter 
with Floppy Disk, Serial and Parallel Adapters.

The information contained herein is largely unique to this document with 
the exception of parts of Appendices 1, 2 & 3 which expand on the 
information contained in the PC1512 User Instructions and the Microsoft 
MSDOS Reference Manual.

Whilst the PC1512 implements a superset of the Industry Standard, this 
manual makes no attempt to identify those areas of the PC1512 
specification which exceed the Industry Standard. Users should, 
therefore, exercise caution when writing software for a range of 
manufacturers' PCs and only use the "Lowest Common Denominator" 
facilities if simple portability is required.

ALL correspondence should be addressed to:-

01277-230232   01277-262326    AMSTRAD Consumer Electronics Plc
01277-230222   01277-209508            Brentwood House         
0898-808181    01277-236100             169 Kings Road         
0891-808181  (premium line)               Brentwood            
                                        ESSEX CM14 4EF         

Written by Bill Weidenauer, AMSTRAD Consumer Electronics Plc
Published by AMSTRAD. First Published 1986.

MS-DOS(R) is a registered trademark of Microsoft(R) Corporation
DOS Plus is a registered trademark of Digital Research Inc
AMSTRAD PC1512 is a trademark of AMSTRAD Consumer Electronics Plc

AMSTRAD is a registered trademark of AMSTRAD Consumer Electronics Plc
Unauthorised use of the trademark or word AMSTRAD is strictly forbidden

Table of Contents:

Section 1 - Hardware.

1.0         Introduction
1.1         CPU
1.2         Memory Layout
1.3         Main Board I/O Channels
1.4         Expansion Bus I/O Channels
1.5         DMA
1.5.1       DMA Page Registers
1.5.2       DMA Initialisation
1.6         System Interrupts
1.6.1       Interrupt Levels
1.6.2       Interrupt Controller initialisation
1.6.3       NMI Mask Control
1.7         Programmable Interval Timers
1.7.1       Timer Configuration
1.7.2       Counter 1 Initialisation
1.8         System Status and Control
1.8.1       Port B - System Control
1.8.2       Port A - Status-1 Input/Keyboard Code
1.8.3       Port C - Status-2 Input
1.8.4       Write System Status-1
1.8.5       Write System Status-2
1.8.6       System Reset
1.9         Real Time Clock
1.10        parallel Printer Port
1.10.1      Printer data Latch
1.10.3      Printer Status Channel
1.10.2      Printer Control Latch
1.11        Alpha/Graphics Colour VDU Controller
1.11.1      Alpha Display
1.11.2      Graphics Display
1.11.2.1    Graphics Mode 1
1.11.2.2    Graphics Mode 2
1.11.3      VDU Control Registers
1.11.3.1    VDU Mode Control Register
1.11.3.2    VDU Colour Select Register
1.11.3.3    VDU Colour Plane Write Register
1.11.3.4    VDU Colour Plane Read Register
1.11.3.5    VDU Graphics Mode 2 Border Register
1.11.4      Status Register
1.11.5      MC6845 CRTC Emulation
1.11.6      CRTC Display Addressing
1.11.6.1    Mode Mapping Relationships
1.11.6.2    Display RAM Access Overhead
1.11.6.3    Alpha Mode Character Generator ROM
1.12        Floppy Disk Controller
1.12.1      FDC Hardware Conditions
1.13        RS232 Asynchronous Serial Port
1.13.1      Serial Channel Interface
1.13.2      Serial Channel Pin Arrangement
1.14        Printer Parallel Port
1.15        Keyboard Interface
1.15.1      Serial Clock and Serial data
1.15.2      Keyboard to Main Board Interface
1.15.3      Main board to Keyboard Interface
1.15.4      Keycodes
1.15.5      Keyboard Connector
1.16        Mouse Interface
1.16.1      Mouse Connector
1.17        Joystick Interface
1.17.1      Joystick Connector
1.18        Light Pen Connector
1.19        Expansion Card Interface
1.20        Video Connector
1.21        Power Connector

Section 2 - Firmware

2.0         Interface
2.1         Power-Up Initialisation and Self Test
2.2         Power-Up Self Tests
2.2.1       Test Procedure
2.2.2       Test Methods
2.2.3       ROS Checksum Test
2.2.4       VDU RAM and VDU Controller Test
2.2.5       Direct Memory Access Controller Test
2.2.6       Programmable Interval Timer Test
2.2.7       Programmable Peripheral Interface Test
2.2.8       Real Time Clock Test
2.2.9       Asynchronous Communications Element Test
2.2.10      Printer Parallel Port Test
2.2.11      Mouse X and Y Count Register Test
2.2.12      System RAM Test
2.2.13      Programmable Interrupt Controller Test
2.2.14      Disk Test
2.2.15      Keyboard Interface Test
2.3         ROS Interrupts
2.3.1       Interrupt 2: Parity Error (NMI)
2.3.2       Interrupt 5: Print Screen
2.3.3       Interrupt 6: Mouse Button Control
2.3.4       Interrupt 8: System Clock Interrupt
2.3.5       Interrupt 9: Keyboard Interrupt
2.3.5.1     Special Key Actions
2.3.6       Interrupt 14: Floppy Disk Controller
2.3.7       Interrupt 16: VDU I/O
2.3.8       Interrupt 17: System Configuration
2.3.9       Interrupt 18: Memory Size
2.3.10      Interrupt 19: Disk I/O
2.3.11      Interrupt 20: Serial I/O
2.3.12      Interrupt 21: Enhanced Function Interrupt
2.3.13      Interrupt 22: Keyboard I/O
2.3.14      Interrupt 23: Printer I/O
2.3.15      Interrupt 24: System Restart
2.3.16      Interrupt 25: Disk Bootstrap
2.3.17      Interrupt 26: System Clock & Real Time Clock
2.3.18      Interrupt 27: Keyboard Break Interrupt
2.3.19      Interrupt 28: External Ticker Interrupt
2.3.20      Interrupt 29: VDU parameter Table
2.3.21      Interrupt 30: Disk Parameter Table
2.3.22      Interrupt 31: VDU Matrix Table
2.4         RAM Variables
2.5         Non-Volatile RAM
2.6         ROS Messages
2.6.1       Non-fatal ROS Messages
2.6.2       Fatal Messages
3.1         Language Links
3.2         Processor Memory Usage
3.3         Keyboard and Key Codes
3.4         Asynchronous Communication Element (8250) Registers
3.5         High Performance DMA Controller (8237A-4) Registers
3.6         Programmable Interrupt Controller (8259-A) Command Words
3.7         Programmable Interval Timer (8253) Registers
3.8         Real Time Clock (HD146818) Registers
3.8.1       Time Calendar & Alarm Locations
3.8.2       RTC Register Locations
3.0         Floppy Disk Controller (uPD765A)

Appendices

1           Mouse Software Interfaces
2           MS-DOS System Configuration
2.1         BREAK Command
2.2         BUFFERS Command
2.3         COUNTRY Command
2.4         DEVICE Command
2.5         DRIVPARM Command
2.6         FCBS Command
2.7         FILES Command
2.8         LASTDRIVE Command
2.9         SHELL Command
2.10        KEYBUK Command
3           Country Dependent Information for MS-DOS 3.2
4           RS232 Connections
5           Printer Lead (PL-2) Wiring Specification
6           Power Supply Requirements
7           ROM Character Set
8           Keyboard Keycodes
9           Keyboard Layouts
9.1         UK Keyboard
9.2         US Keyboard
9.3         French Keyboard
9.4         German Keyboard
9.5         Spanish Keyboard
9.6         Italian Keyboard
9.7         Danish Keyboard
9.8         Swedish Keyboard

SECTION 1 - HARDWARE
====================

1.0 Introduction

This manual provides a comprehensive description of the AMSTRAD PC 1512 
hardware and firmware. General information about the PC1512, GEM Desktop 
and the delivered operating system software is contained in the AMSTRAD 
PC USER MANUAL. This manual is intended to satisfy the needs of advanced 
developers who must have access to the various resources available 
within the PC1512.

1.1 Central Processing Unit (CPU)

The CPU is an 8086-2 microprocessor with 1 Megabyte memory addressing 
capability (see Figure 1.1), running at a clock frequency of 8 MHz. The 
CPU is connected to an on-board 16-bit system memory bus requiring four 
125nS timimg cycles (T-States) per access resulting in a 500nS memory 
cycle for 16-bit memory. The CPU is also connected to an on-board 8-bit 
I/O and memory peripheral bus with a 4 MHz clock, which in turn connects 
to an external (off-board) expansion bus. Operations on the 8-bit bus 
automatically incur 125nS wait states as follows:

Operation                       Wait States             Bus Cycle
8-bit (Memory)                       4                     1.0S
16-to 8-bit convert (Memory)        12                     2.0S
8-bit (I/O)                          6                     1.25S
16-to 8-bit (I/O)                   16                     2.5S
                                               

The CPU is configured to run in maximum mode and the instruction set may 
be optionally extended by the addition of an 8087-2 Numeric Data 
Coprocessor. The 8087 BUSY output is connected directly to the 8086 NOT 
TEST input.

1.2 MEMORY LAYOUT

The main board memory consists of 512K bytes of system RAM with parity 
checking and 16K bytes os system ROM without parity checking. Note that 
all address constants in this document are in hexadecimal format except 
as noted.

The 512K byte user RAM starts at CPU memory address 00000 and extends to 
7FFFF. An additional 128K bytes may be added externally in 32K byte 
blocks on the address space from 80000 to 9FFFF to extend the total 
system RAM to 640K bytes, provided the 640K byte option is not already 
installed on-board.

The 128K byte address space from A0000 to BFFFF is reserved for the 8-bit 
memory associated with certain controllers, and is not used by CPU 
programs. The on-board Alpha/Graphics VDU controller uses the 16K byte 
address range from B8000 to BBFFF for screen refresh memory. Also an 
optional external monochrome alphanumeric VDU controller uses the 4K 
memory address range from B0000 to B0FFF.

The 192K byte address space from C0000 to EFFFF is reserved for external 
expansion ROM address space. The optional Hard Disk Controller uses the 
16K byte address range from C8000 to CBFFF.

The 16K byte system ROM is at FC000 to FFFFF and contains the Resident 
Operating System (ROS) firmware. The 48K address range from F0000 to 
FBFFF is reserved for ROM space expansion.

                       FIGURE 1.1 - MEMORY LAYOUT


 FFFFF                                               
        FC000        RESIDENT OPERATING SYSTEM ROM         64K BYTE
       Ĵ       SYSTEM
       FBFFF            48K BYTES RESERVED                ROM AREA
       F0000                                        
       
       EFFFF         192K BYTES EXPANSION ROMS      
       C0000            C8000-CBFFF: HD ROM         
       Ĵ
        BFFFF             128K BYTES                 
1M BYTE               8-BIT CONTROLLER MEMORY        
ADDRESS               B8000-BBFFF: VDU SCREEN              
 RANGE  A0000         A0000-BFFFF: EGA SCREEN              
        
       9FFFF             128K BYTES                 
                    ADDITIONAL USER MEMORY          
       80000      (EXTERNAL 32K BYTE BLOCKS)              640K BYTE
       Ĵ     USER MEMORY
       7FFFF             512K BYTES                         RANGE
                           ON-BOARD                  
 00000                     USER RAM                  

                                   8

                                Fig 1.2                                  Ŀ
                                                                        Ŀ
                                                                       Ŀ
                                                                ڮįEXP
 Ŀ       Ŀ  Ŀ                 8-bit data bus              BUS
 Mo       Sp                   į      
 us       ea   NDP               (Add., Data, Control)         Ŀ
 e        ke   8081                                      įPRI
          (opt)                                            PRT
                                                                 
   Ŀ                       Ŀ                 Ŀ
 AMEM                                         įSIO
 d  GATE                                                        825
 dگARRAYĿ  Ŀ         Ŀ       Ŀ              
 r                                                         Ŀ
 e             CPU           BUS         VDU  ͻ  įRTC
 s             8086į GATE   į GATEïVDU           
 s        8MHz        ARRAY       ARRAY ͼ        
 , Ŀ data                                               Ŀ
  ïRAMĴ                                        įDMA
 C                                         
 o Ŀ data 16 bit data                    Ŀ               
 nïRAM             įROM               Ŀ
 t       (Add., Data, Cont.)                      įPIT
 r Ŀ data     Ŀ                       Ŀ                  
 oROS    JOYĿ           įVDU               
 l                 Ŀ    RAM               Ŀ
 s                               KEYBOARD                įPIC
                                                        
                                                                      
                                                                      Ŀ
                                                                įFDC
                                                                          
                                                                       

1.3 MAIN BOARD I/O CHANNELS

The interfaces on the main board occupy the 8086 I/O addresses as follows:

ADDRESS(hex)     OUTPUT USE                      INPUT USE

000-00F          8237 DMA Controller             8237 DMA Controller
010-01F          Do Not Use                      Do Not Use
020-021          8259 Interrupt control          8259 Interrupt control
022-03F          Do Not Use                      Do Not Use
040-042          8253 PIT Load Count (0-2)       8253 PIT Read Count (0-2)
043              8253 PIT Load Mode              Undefined
044-05F          Do Not Use                      Do Not Use
060              No Effect                       Port A - Keyboard Code or
                                                    System Status - 1
061              Port B - System Control         Port B - (Readback)
062              No Effect                       Port C - System Status - 2
063              No Effect                       Do Not Use
064              Write System Status - 1         Do Not Use
065              Write System Status - 2         Do Not Use
066              System Reset                    Do Not Use
067-06F          Do Not Use                      Do Not Use
070              146818 RTC Address              Do Not Use
071              146818 RTC Data                 146818 RTC Data
072-077          Do Not Use                      Do Not Use          
078              Clear Mouse X-Coordinate        Mouse X-Coordinate
079              Do Not Use                      Do Not Use
07A              Clear Mouse Y-Coordinate        Mouse Y-Coordinate
07B-07F          Do Not Use                      Do Not Use
080              Do Not Use                      Do Not Use
081              DMA Page Register Ch 2          Do Not Use
082              DMA Page Register Ch 3          Do Not Use
083              DMA Page Register Ch 0,1        Do Not Use
084-09F          Do Not Use                      Do Not Use
0A0              NMI Mask Control                Do Not Use
0A1-0BF          Do Not Use                      Do Not Use


ADDRESS(hex)     OUTPUT USE                      INPUT USE

378              Printer Data Latch              Printer Data Latch
379              Do Not Use                      Printer Status
37A              Printer Control Latch           Printer Control Latch
37B-37F          Do Not Use                      Do Not Use
3D0              CRTC Address Register           Do Not Use
3D1              CRTC Data                       CRTC Data
3D2-3D7          Do Not Use                      Do Not Use
3D8              VDU Mode Control                Do Not Use
3D9              VDU Mode Select                 Do Not Use
3DA              Do Not Use                      VDU Status
3DB              Clear Light Pen Latch           Do Not Use
3DC              Set Light Pen Latch             Do Not Use
3DD              VDU Colour Plane Write          Do Not Use
3DE              VDU Colour Plane Read           Do Not Use
3DF              VDU Graphics Mode 2 Border      Reserved
3F0-3F1          Do Not Use                      Do Not Use
3F2              Drive Selection                 Do Not Use
3F3              Do Not Use                      Do Not Use
3F4              Do Not Use                      765 FDC Status
3F5              765 FDC Data                    765 FDC Data
3F6-3F7          Do Not Use                      Do Not Use
3F8-3FF          8250 UART Tx Data/Control       8250 UART Rx Data/Control
                                              
                                              

Note: I/O addresses above 3FF, if accessed, wrap around and are mapped onto 
      the range 000-3FFF. Any of the unlisted addresses may be used in the 
      future.

1.4 EXPANSION BUS I/O CHANNELS

The 8086 CPU I/O addresses on the expansion bus are as follows:


ADDRESS(hex)       USE

200-20F            External Game Control Interface
210-217            External Bus Extension Unit
278-27F            External Printer Port
2B0-2DF            External Secondary Enhanced Graphics Controller
2F8-2FF            External Asynchronous Serial RS232C Port
300-31F            External Prototyping Card
320-32F            External hard Disk Controller
380-38C            External SDLC Serial RS232C Port or Extended BSC Controller
390-393            External Cluster Controller
3B0-3BB            External Monochrome VDU Controller
3BC-3BF            Printer Port
3C0-3CF            External Graphics Controller
               
I/O Addresses wrap around above 3FF occurs as described on page 10.

External cluster controllers at 790-793, B90-B93, 1390-1398 & 2390-2393 
wrap around to I/O addresses 390-393.

1.5 DIRECT MEMORY ACCESS (DMA)

The AMSTRAD PC supports 4 DMA channels on the system board using an 8237-4 
DMA controller and programmable page registers to extend its addressing 
range from 64K bytes to 1M bytes. Each channel is able to transfer data in 
blocks of up to 64K bytes within a page. The DMA channels are for 8-bit 
data transfers between (8-bit) I/O devices and 8-bit or 16-bit memory.

In peripheral (slave) mode,CPU I/O addresses lines A0-A3 are connected 
conventionally so that 16 command codes appear in the order described in 
the 8237 data sheets (See section 3.5).

The DMA controller CLK is driven at 4 MHz (0.1%). In master mode during 
DMA transfers on channels 1,2 and 3, one wait state is added resulting in a 
five-clock DMA bus cycle of 1.25S. Channel 0 transfers have a four-clock 
bus cycle of 1S.

The DMA channel request signals are as follows:


 DMA                
Channel             USE

   0     8253 Timer/Counter OUT1 output - for memory refresh.
   1     Spare for use by expansion bus. Used by external SDLC Serial Port.
   2     765 Floppy Disk Controller DRQ output. Available on the expansion bus.
   3     Spare for use by expansion bus. Used by external Hard Disk Controller.
        

1.5.1 DMA Page Registers

DMA channels 1,2 and 3 can address the entire 1M addressing range of the 
8086 CPU through the use of their associated DMA page registers. There are 
three DMA registers, one each for channels 1 through 3. Each page register 
defines for its channel which one of 16 64K byte pages in the 1M byte 
address range DMA transfers are to occur. The page registers are static so 
that modulo 64K byte addressing occurs at page boundaries. They are located 
in the I/O address space in the range 081-083.

The DMA page register bit assignments are as follows:

 Bit         Output Use

  7          Not Connected
  6          Not Connected
  5          Not Connected
  4          Not Connected
  3          Address bit A19
  2          Address bit A18
  1          Address bit A17
  0          Address bit A16
        

1.5.2 DMA Initialisation

Following a reset, system initialisation firmware (in the ROS) sets up the 
8237 for channel 0 (dynamic RAM refresh) operation as follows:


   Function          Initialised State

   Word Count        64K Transfers
                
   Mode              Read
   Register          Autoinitialise
                     Increment
                     Single Mode
                
   Command           Disable Memory to Memory
   Register          Enable Controller
                     Normal Timing
                     Fixed Priority
                     Late Write
                     DREQ Active High
                     DACK Active Low
                
   Mask              Clear Channel 0 Mask Bit
   Register     
                

After power-up or system reset the DMA page registers are undefined and are 
initialised to zero by the ROS firmware and all 8037 internal locations for 
channels 1-3 are initialised to a state comparable to the channel zero 
initialisation above. 

Following industry compatibility, memory to memory DMA is not supported on 
the PC1512. It is prohibited due to timing considerations.

1.6 System Interrupts

Nine levels of hardware interrupt are provided for in the system by the CPU 
Non Maskable Interrupt (NMI) and by an 8259A-2 Interrupt Controller. All 
levels including NMI, are maskable under software control.

CPU I/O address line A0 is connected conventionally so that the command 
codes appear in the order described in the 8259 data sheets. The SP/EN pin 
is tied high signifying that the device is to be hardware un-buffered and 
designated as a master, not a slave.

1.6.1 Interrupt Levels

The interrupt levels are assigned as follows:


   Level             Assigned Function

   NMI               Memory Parity Error and 8087 NDP INT output.
                
    0                8253 Timer/Counter Out0 output.
                
    1                Keyboard Scan Code Receiver.
                
    2                146818 Real Time Clock IRQ output.
                     Available on expansion bus.
                     May be used by Enhanced Graphics Adapter.
                
    3                Spare for use by expansion bus.
                     Used by external (secondary) Asynchronous Serial
                          Port and external SDLC Serial Port.
                
    4                8250 UART INTRPT output.
                     Available on expansion bus.
                     Used by external SDLC Serial Port.
                
    5                Spare for use by expansion bus.
                     Used by external Hard Disk Controller.
                
    6                765 Floppy Disk Controller INT output.
                     Available on the expansion bus.
                
    7                Parallel Printer Port.
                     Available on the expansion bus.
                     Used by external Printer Port (secondary) Printer
                     Port (tertiary), external Monochrome VDU Controller,
                     and external cluster controllers.
                

1.6.2 Interrupt Controller Initialisation

Following a reset, the initialisation firmware in the ROS sets the 8259 
Interrupt Controller to operate as follows:

                    8086 system,
                    Single (not cascaded),
                    Normal fully nested (not special),
                    Edge-triggered,
                    Buffered mode - slave
                    Normal EOI (not auto),
                    Fixed priority - level 0 highest, level 7 lowest.

1.6.3 NMI Mask Control

This NMI Mask Control is a write only register at I/O address 0A0 and 
allows the CPU non-maskable interrupt (NMI) to be enabled or disabled by 
software. The bit assignment is as follows:


   Bit               Output Use       

    7                Enable NMI
    6 - 0            Not Connected
                

Following a reset NMI is disabled.

NMI can be connected to the 8087 NDP, the on-board memory parity check 
circuit, and the expansion bus I/OCHCK (I/O Channel Check).

1.7 Programmable Interval Timers

Three programmable timer/counters are provided at I/O Addresses 040 - 043 
by an 8253 Programmable Interval Timer (PIT) device. They are defined as 
follows:

   Counter           Use
 
    0                General Purpose Timer.
    1                Used by DMA channel 0 (for dynamic ram refresh)
    2                Tone Generation for Speaker
                

1.7.1 Timer Configuration

The 8253 timers are configured as follows:

   Function          Configuration
 
    CLK 0,1,2        1.193 MHz (0.1%)  
    GATE 0,1         Always 'ON'
    GATE 2           Controlled via Port B (system Control Channel)
                     Speaker Modulate output.
    OUT 0            Interrupts on 8259 PIC IR0 input.
    OUT 1            Requests on 8237 DMA DREQ0 input.
    OUT 2            Logical 'AND' with Port B (System Control Channel)
                     Speaker Drive output. Also goes to Port C 
                     (System Status-2 Channel) as an input.
                

1.7.2 Counter 1 initialisation

Following a reset, the system initialisation firmware in the ROS programs 
the 8253 PIT for counter 1 (dynamic ram refresh) operation as a rate 
generator producing a signal with a period of 13.133S. There are no 
restrictions requiring the initialisation and programming of counters 0 and 2. 

1.8 System Status and Control

Two system status input channels and four output channels are provided on-
board. Ports A,B and C emulate a pre-programmed 8255 PPI device. They are 
located in the I/O address space in the range 060-06F. Port B is programmed 
for control output, Port A is programmed either for Status-1 input or for 
receiving data from the keyboard, and Port C is programmed for Status-2 
input.

Ports A,B and C emulate an 8255 PPI that has been set up as follows:

     Group A Mode 0,                Group B Mode 0,
     Port A = input,                Port B = output,
     Port C(U) = input.             Port C(L) = input.

Unlike an 8255, power-up and reset do not affect this configuration.

1.8.1 Port B - System Control

The System Control channel is located at I/O Address 061. Its bit 
assignment is as follows: 


   Bit (PBn)         Output Use   
 
        7            Enable Status-1 / Disable Keyboard Code on Port A.
        6            Enable incoming Keyboard Clock.
        5            Prevent external parity errors from causing NMI.
        4            Disable parity checking of on-board system Ram.
        3            Undefined (Not Connected)
        2            Enable Port C LSB / Disable MSB. (See 1.8.3)
        1            Speaker Drive.
        0            8253 GATE 2 (Speaker Modulate).
                

When bit 7 is set high (1), Status-1 data is enabled on Port A, the 
keyboard data path and keyboard interrupts are disabled. When bit 7 is set 
low (0), keyboard input data is enabled on Port A, the keyboard data path 
and keyboard interrupts are enabled.

The keyboard interface operates as follows: Each incoming keycode is 
latched on-board causing a keyboard interrupt (on level 1). While the 
interrupt remains pending, the incoming keyboard data signal is forced low 
as an acknowledgement to the keyboard that the keycode has been received. 
As soon as the interrupt has been cleared, the keyboard may use the Data 
signal to transmit the next keycode.

PB1 may be toggled to drive the speaker with a corresponding pulse train. 
The speaker may also be driven by a wave form from the 8253 PIT OUT2 output 
(simultaneously with PB1, if required).

PN0 may be toggled to drive the 8253 gate input, hence modulate counter 
operations and therefore the speaker with a corresponding waveform. Thus 
there are three different methods of driving the speaker which may all be 
performed simultaneously to create various audio effects.

1.8.2 Port A - Status-1 Input / Keyboard Code

Port A is a read only location located at I/O address 060. When PB7 is set 
to high (1) reading Port A loads Status-1. When PB7 is set low (0) reading 
Port A loads the keyboard data. The bit assignments for port A are as 
follows:


   Bit (PAn)         Status-1                               Keyboard Input 

       7             Always 0                                KBD7
       6             Second Floppy disk drive installed.     KBD6
       5             DDM1 - Default Display Mode bit 1.      KBD5
       4             DDM0 - Default Display Mode bit 0.      KBD4
       3             Always 1.                               KBD3
       2             Always 1.                               KBD2
       1             8087 NDP installed.                     KBD1
       0             Always 1.                               KBD0
                                                         

The Default Display Mode bits (DDM1, DDM0) are set up by the ROS during 
system initialisation based on Non-Volatile Ram (NVR) selections as 
follows:

01 (1) Colour, alpha. 40 X 25 chars, Bright white on black.

10 (2) Colour, alpha. 80 X 25 chars, Bright white on black.

11 (3) External Monochrome controller, 80 X 25 chars.

Following a reset, the hardware selects VDU mode 2. The ROS then sets VDU 
state based on the DDM value.

1.8.3 Port C - Status-2 Input

Port C is a read only location at I/O address 062. Its bit assignments are 
as follows:

   Bit (PCn)         Input Use
 
     7               On-board system RAM parity error
     6               External parity error (I/OCHCK from expansion bus).
     5               8253 PIT OUT2 output.
     4               Undefined (Not Connected)

                     LSB        or     MSB (depends on PB2))

     3               RAM3             Undefined
     2               RAM2             Undefined
     1               RAM1             Undefined
     0               RAM0             RAM4
                                

PC7 is forced to the zero state when on-board system RAM parity checking is 
disabled by PB4.

When the I/Ochck condition (external parity error) from the expansion bus 
is disabled from causing NMI (by PB5 set high), PC6 reflects the state of 
the I/OCHCK input else it reflects the latched state of I/OCHK.

The value of RAM4-RAM0 denotes the amount of system RAM fitted to the 
system as follows:

RAM4 RAM3 RAM2 RAM1 RAM0

 0    1    1    1    0        512K bytes on-board.
 0    1    1    1    1        544K bytes (32K external).
 1    0    0    0    0        576K bytes (64K external). 
 1    0    0    0    1        608K bytes (96K external). 
 1    0    0    1    0        640K bytes (128K external or fitted on board). 

1.8.4 Write System Status-1

The Write System Status-1 register is a write only register at I/O address 
064 and is initialised by the Resident Operating System (ROS) firmware 
based on values obtained from the Non-Volatile Ram (NVR). It is used in 
conjunction with the 8255 PPI Port A emulation. The bit assignments are as 
follows:


   Bit               Output Use
 
    7                No Effect.
    6                PA6 - Second floppy disk drive installed.
    5                PA5 - DDM1.
    4                PA4 - DDM0.
    3                No Effect.
    2                No Effect.
    1                PA1 - 8087 NDP installed.
    0                No Effect.
                

1.8.5 Write System Status-2

The Write System Status-2 register is a write only register at I/O Address 
065 and is initialised by the Resident Operating System (ROS) firmware 
based on values obtained from the Non-Volatile Ram (NVR). It is used in 
conjunction with the 8255 PPI Port C emulation. The bit assignments are as 
follows:

   Bit               Output Use

    7                PC2 (MSB) - Undefined.
    6                PC1 (MSB) - Undefined.
    5                PC0 (MSB) - Undefined.
    4                PC3 (MSB) - RAM4.
    3                PC3 (LSB) - RAM3.
    2                PC2 (LSB) - RAM2.
    1                PC1 (LSB) - RAM1.
    0                PC0 (LSB) - RAM0.
                

1.8.6 System Reset

Any write access to I/O Address 066 regardless of the value written will 
cause the hardware to generate an immediate 512S system reset and pulse 
the reset line on the expansion bus. The contents of the on-board system 
RAM is preserved following a system reset.

1.9 Real Time Clock

HD146818 Real Time Clock plus Ram device is installed and backed up by a 
set of four non-rechargable size AA batteries. The clock device provides a 
time of day clock with alarm, a one hundred year calendar, a programmable 
periodic interrupt, and 50 bytes of static RAM. The static RAM is called 
the Non-Volatile Ram (NVR) and is used to store system configuration data 
such as number of disk drives, memory size, serial I/O parameters, and 
default VDU screen mode. The ROS firmware maintains a checksum of the NVR 
and will reset the configuration data to "sensible values" during startup 
whenever the checksum value is incorrect (thus destroying your actual 
configuration). Even though direct hardware access to the NVR is possible 
it is recommended that the programs make use of the ROS Enhanced Function 
Interrupt (Interrupt 21) to access the NVR because these properly maintain 
the NVR checksum value.

When system power is off and the 146818 is on battery backup power, the 
functions which remain active are the clock and the retention of RAM data. 
No battery power is used while the system power is on.

The input crystal oscillator runs at 32.768 KHz.

The 146818 interrupt request is connected to the 8259 system interrupt 
controller on level 2 (which as also available on the expansion bus). The 
146818 power-sense input PS is connected to a battery condition sensor. 
When the backup battery voltage is sufficiently low, the VRT bit in 
register D becomes set indicating that the time, the calendar and the NVR 
data are no longer valid. When this condition is noted during startup, the 
firmware outputs the message "Please fit new batteries" and resets the NVR 
to default values (see section 2.4).

All the features described in the 146818 data sheet are available with the 
exception that the CKOUT (clock output) and SQW (square wave output) pins 
are not connected on the main board.

Writing or reading the NVR involves a two step sequence for each byte that 
is accessed. The RTC Address channel (I/O Address 070) is first loaded with 
the NVR location to be accessed. Then the RTC data channel (I/O Address 
071) is either written or read to complete the I/O operation. This facility 
should be used with caution in order to avoid disturbing the system 
configuration data.

1.10 Parallel Printer Port

The printer port provides an interface for driving 8-but and 7-bit 
Centronics compatible printers. The timing of the signals to the printer is 
under direct software control. There is a read/write control latch for 
sending control signals to the printer, an unlatched read-only printer 
status channel, and a read/write data latch for sending printer data.

1.10.1

The printer data latch is a read/write register at I/O address 378 and its 
layout is as follows:


   Bit (Dn)          Output/Input Use      Cable Polarity 

     7                  Data 7                  Hi
     6                  Data 6                  Hi
     5                  Data 5                  Hi
     4                  Data 4                  Hi
     3                  Data 3                  Hi
     2                  Data 2                  Hi
     1                  Data 1                  Hi
     0                  Data 0                  Hi
                                        
The contents of the data latch are undefined following a power-up or system 
reset.

1.10.2 Printer Control Latch
    
The printer control latch is a read/write register at I/O address 37A and 
its layout is as follows:

   Bit       Output/Input Use      Reset State     Cable Polarity

   7-5       No effect                           
    4        Enable Int on ACK     False         
    3        Select Printer        False              Lo
             _____________                       
    2        Reset Printer         True               Lo
    1        Select Auto Feed      False              Lo
    0        Data Strobe           False              Lo
                                                 

When Interrupt on ACK is enabled an incoming Printer Acknowledge condition 
will cause a system interrupt on level 7 (which is also available on the 
expansion bus).

If the printer control lines normally driven via latch bits D0-D3 are 
driven externally, the data read on input to the channel will be the 
logical OR of the latched bits and the externally driven bits. e.g. If a 
data bit is false and the corresponding cable bit is driven true by the 
external driver, the bit input will be true.

Following power-up or system reset, the control latch contents assume reset 
conditions as shown.

Note that this is a general purpose printer interface and that not all 
printers require all the control signals, hence the provision for non-
standard printers to be able to drive some of the control signals as inputs 
to the main board. The timing requirements on Centronics compatible 
printers generally specify that data must be present at 1S before the 
strobe is made active, and must remain valid for at least 1S after strobe 
goes inactive. The strobe duration must be between 1S and 500S. Printer 
Busy status can be inspected as soon as the strobe is inactive in order to 
determine when more data can be sent.

1.10.3 Printer Status Channel

The Printer Status Channel is a read only register at I/O Address 379 
(hex). Its layout is as follows:

   Bit (Dn)          Input Use                 Cable Polarity

                     ____________           
    7                Printer Busy               Hi
                     ___________________    
    6                Printer Acknowledge        Lo
                                            
    5                Paper Out                  Hi
                                            
    4                Printer Selected           Hi
                     _____________          
    3                Printer Error              Lo
                     __________             
    2                LK3 Fitted             
                     __________             
    1                LK2 Fitted             
                     __________             
    0                LK1 Fitted             
                                            

LK1-LK3 are general purpose factory installed option links on the main 
board which are used by the firmware to distinguish different machine 
configurations. The first seven states (0-6) are used for language variants 
and the all ones (7) state is used for Power-Up Self Test Maintenance Mode 
(See section 2.2).

Note that this is a general purpose printer interface and that not all 
printers implement all the status lines, nor do they all attach the same 
meaning to the status conditions.

Printer Busy normally indicates that a printer cannot receive data, for 
example during data entry, printing, when offline, or during a printer 
error condition.

Printer Acknowledge, if implemented is generally asserted by a printer to 
indicate that data has been received and the printer is ready to receive 
the next data. Note that Printer Acknowledge (ACK) can also be set to cause 
an interrupt (See 1.10.2).

Section 1.14 contains the printer connector pin assignments.

