2.3 ROSS Interrupts.

The first 32 interrupt vectors are initialised by Power-Up 
initialisation. The software IRET and hardware HWIRET entries are dummy 
routines which require no entry or exit conditions and are not detailed 
here.

Any application program which replaces a default interrupt vector with 
its own entry point must not invoke any ROS interrupt within its own 
interrupt service routine.

2.3.1 INTERRUPT 2: Parity Error (NMI). The Interrupt 2 routine deals 
with system RAM parity error. The screen is switched to the default 
display mode, cleared and a RAM parity error message is displayed. The 
machine cannot be used until the power switch is cycled off and on 
again.

This routine does not use RAM for stack or program variables.

An application program which makes use of the 8087 NDP must supply an 
interrupt 2 service routine for the 8087 NDP.

CPU registers are used as follows:

Entry:  No conditions.
Exit:   Doesn't exit.

2.3.2 INTERRUPT 5:Print Screen.

The Interrupt routine dumps the screen in character mode to the primary 
printer port. Since the screen dump is character based, attempting to 
dump graphic pictures to the printer may produce incorrect results. 
Characters that cannot be read back to the screen in graphics mode 
(using the VDU interrupt read character sub-function) are printed as 
spaces.

If a screen print is already in progress then the interrupt takes no 
action.

The Print Screen Status variable (at address 0500) is set to 1 while the 
screen dump is in progress. When complete the variable is set to zero. 
If the screen dump is abandoned due to printer port timeout, the 
variable is set to 255.

CPU registers are used as follows:

Entry:  No conditions.
Exit:   All flags and registers preserved.

2.3.3 INTERRUPT 6: Mouse Button Control.

The ROS interrupt 6 routine provides default mouse button services. The 
keyboard firmware generates a set of make/break keycodes when either of 
the two mouse buttons is pressed and released. When the keyboard 
interrupt routine recognizes a mouse button keycode it invokes 
interrupt 6. The default ROS routine will either obtain the appropriate 
keycode from the NVR and return with the carry flag set in the case of a 
make code or return with the carry flag clear in response to a mouse 
button break code.

CPU registers are used as follows:

Entry:  Register AL = Mouse Key Code

        Bit 0 specifies which mouse button:

            0 = Mouse Button M1.
            1 = Mouse Button M2.

        Bit 7 specifies whether make or break:

            0 = Mouse Button make.
            1 = Mouse Button break.

Exit: Carry Flag & Register Ax specify action:

      Carry SET:  Insert a key token into the keyboard buffer.
                  AX = key Token to be inserted.

      Carry CLEAR:No action to be taken.
                  AX is corrupt.

      All other flags corrupt. (also BX, CX & DX may be corrupt)
      All other registers preserved.

Note: A key token value of FFFFh is ignored and is not put in the 
keyboard buffer.

2.3.4 INTERRUPT 8: System Clock Interrupt.

The interrupt 8 routine is invoked by the system clock (counter 0 of the 
8253). The default ROS routine does the following:

1. Increment the 32-bit system clock count held in RAM (location 0046C). 
If the clock reaches the 24 hour time (0001855000h) then the count is 
reset to zero and the 24 hour flag (location 00470) is set to 0FFh.
 
2. If the least significant byte of the system clock count is zero then 
the current time and date in the real time clock (RTC) is copied to the 
NVR. The time that is last copied from the RTC before the machine is 
switched off is displayed when the machine is next switched on.

3. If the disk motor timeout count is not zero then it is decremented by 
one. If the count reaches zero all the drive motors are turned off.

4. Invoke interrupt 28. Application programs that want to be interrupted 
by the system clock should use interrupt 28.

CPU registers are used as follows:

Entry:  No conditions.
Exit:   All flags and registers preserved.

2.3.5 INTERRUPT 9: Keyboard Interrupt.

The ROS Keyboard hardware interrupt reads a key code from the keyboard 
interface, translates the key code into a 16-bit key token using an 
internal translation table and the key token is put into the key token 
buffer. If the buffer is full the key token is discarded and a bleep is 
output on the speaker.

Entry:  No conditions.
Exit:   All flags and registers preserved.

The ROS Keycode translation table is as follows (all values are 
hexadecimal):

Key Code  (UK) Key Name  Normal     ALT     CTRL    SHIFT    Num Lock

  01           ESC        011B    Ignored   011B     011B      N/A  
  02         1 and !      0231     7800    Ignored   0221      N/A
  03         2 and "      0332     7900    Ignored   0340      N/A
  04         3 and       0433     7A00    Ignored   0423      N/A
  05         4 and $      0534     7B00    Ignored   0524      N/A
  06         5 and %      0635     7C00    Ignored   0625      N/A
  07         6 and ^      0736     7D00     071E     075E      N/A
  08         7 and &      0837     7E00    Ignored   0826      N/A
  09         8 and *      0938     7F00    Ignored   092A      N/A
  0A         9 and (      0A39     8000    Ignored   0A28      N/A
  0B         0 and )      0B30     8100    Ignored   0B29      N/A
  0C         - and _      0C2D     8200     0C1F     0C5F      N/A
  0D         = and +      0D3D     8300    Ignored   0D2B      N/A
  0E         <-DEL        0E08    Ignored   0E7F     0E08      N/A
  0F           TAB        0F09    Ignored  Ignored   0F00      N/A
  10            Q         1071     1000     1011     1051      N/A
  11            W         1177     1100     1117     1157      N/A
  12            E         1265     1200     1205     1245      N/A
  13            R         1372     1300     1312     1352      N/A
  14            T         1474     1400     1414     1454      N/A
  15            Y         1579     1500     1519     1559      N/A
  16            U         1675     1600     1615     1655      N/A
  17            I         1769     1700     1709     1749      N/A
  18            O         186F     1800     180F     184F      N/A
  19            P         1970     1900     1910     1950      N/A
  1A         [ and {      1A5B    Ignored   1A1B     1A7B      N/A
  1B         ] and }      1B7D    Ignored   1B1D     1B7D      N/A
  1C           CR<-       1C0D    Ignored   1C0A     1C0D      N/A
  1D          CTRL       Ignored  Ignored   ----    Ignored    N/A
  1E            A         1E61     1E00     1E01     1E41      N/A
  1F            S         1F73     1F00     1F13     1F53      N/A
  20            D         2064     2000     2004     2044      N/A
  21            F         2166     2100     2106     2146      N/A
  22            G         2267     2200     2207     2247      N/A
  23            H         2368     2300     2308     2348      N/A
  24            J         246A     2400     240A     244A      N/A
  25            K         256B     2500     250B     254B      N/A
  26            L         266C     2600     260C     264C      N/A
  27         ; and :      273B    Ignored  Ignored   273A      N/A
  28         ' and @      2827    Ignored  Ignored   2822      N/A
  29         # and ~      2960    Ignored  Ignored   297E      N/A
  2A       LEFT SHIFT    Ignored  Ignored  Ignored   ----      N/A
  2B         \ and |      2B5C    Ignored   2B1C     2B7C      N/A
  2C            Z         2C7A     2C00     2C1A     2C5A      N/A
  2D            X         2D78     2D00     2D18     2D58      N/A
  2E            C         2E63     2E00     2E03     2E43      N/A
  2F            V         2F76     2F00     2F16     2F56      N/A
  30            B         3062     3000     3002     3042      N/A
  31            N         316E     3100     310E     314E      N/A
  32            M         326D     3200     320D     324D      N/A
  33         , and <      332C    Ignored  Ignored   333C      N/A
  34         . and >      342E    Ignored  Ignored   343E      N/A
  35         / and ?      352F    Ignored  Ignored   353F      N/A
  36       RIGHT SHIFT   Ignored  Ignored  Ignored   ----      N/A
  37       * and PrtSc    372A    Ignored   7200   Prnt Scrn   N/A
  38           ALT       Ignored   ----    Ignored  Ignored    N/A
  39         SPACE        3920     3920     3920     3920      N/A
 *3A       CAPS LOCK     Ignored  Ignored  Ignored  Ignored    N/A
  3B           F1         3B00     6800     5E00     5400      N/A
  3C           F2         3C00     6900     5F00     5500      N/A
  3D           F3         3D00     6A00     6000     5600      N/A
  3E           F4         3E00     6B00     6100     5700      N/A
  3F           F5         3F00     6C00     6200     5800      N/A
  40           F6         4000     6D00     6300     5900      N/A
  41           F7         4100     6E00     6400     5A00      N/A
  42           F8         4200     6F00     6500     5B00      N/A
  43           F9         4300     7000     6600     5C00      N/A
  44           F10        4400     7100     6700     5D00      N/A
 *45        NUM LOCK     Ignored  Ignored  PAUSE    Ignored    N/A
 *46      SCROLL LOCK    Ignored  Ignored  BREAK    Ignored    N/A
  47       KEY PAD 7      4700    Ignored   7700      N/A     4737
  48       KEY PAD 8      4800    Ignored  Ignored    N/A     4838
  49       KEY PAD 9      4900    Ignored   8400      N/A     4939
  4A       KEY PAD -      4A2D    Ignored  Ignored    N/A     4A2D
  4B       KEY PAD 4      4B00    Ignored   7300      N/A     4B34
  4C       KEY PAD 5     Ignored  Ignored  Ignored    N/A     4C35
  4D       KEY PAD 6      4D00    Ignored   7400      N/A     4D36
  4E       KEY PAD +      4E2B    Ignored  Ignored    N/A     4E2B
  4F       KEY PAD 1      4F00    Ignored   7500      N/A     4F31
  50       KEY PAD 2      5000    Ignored  Ignored    N/A     5032
  51       KEY PAD 3      5100    Ignored   7600      N/A     5133
 *52     KEY PAD 0 (INS)  5200    Ignored  Ignored    N/A     5230
  53       KEY PAD .      5300    Ignored  Ignored    N/A     532E
54-6F      UNDEFINED     Ignored  Ignored  Ignored  Ignored  Ignored
 *70         DEL->         N/A      N/A      N/A      N/A      N/A
71-73      UNDEFINED     Ignored  Ignored  Ignored  Ignored  Ignored
 *74         ENTER         N/A      N/A      N/A      N/A      N/A
75-76      UNDEFINED     Ignored  Ignored  Ignored  Ignored  Ignored
 *77       JOY FIRE 2      N/A      N/A      N/A      N/A      N/A
 *78       JOY FIRE 1      N/A      N/A      N/A      N/A      N/A
 *79       JOY RIGHT      4D00     4D00     4D00     4D00     4D00
 *7A       JOY LEFT       4B00     4B00     4B00     4B00     4B00
 *7B       JOY DOWN       5000     5000     5000     5000     5000
 *7C       JOY UP         4800     4800     4800     4800     4800
 *7D       MOUSE M2        N/A      N/A      N/A      N/A      N/A
 *7E       MOUSE M1        N/A      N/A      N/A      N/A      N/A
 *7F       UNDEFINED     Ignored  Ignored  Ignored  Ignored  Ignored
                                                               

Joystick keys produce their respective cursor keys. 
Key codes marked with '*' cause special actions as explained on the next 
page. 

2.3.5.1 Special Key Actions.

Some keys or set of keys invoke a special action as detailed below. 
Unless otherwise stated they do not result in any key tokens being 
inserted into the buffer.

1. [CTRL]+[ALT]+[DEL]: Reset

When reset is detected, a system hardware reset is issued. The power-up 
initialisation process is entered but system RAM and VDU RAM are not 
run.

2. [CTRL]+[NUM LOCK]: Pause.

The ROS waits for another key to be pressed (except [CTRL]+[NUM LOCK], 
thus suspending any application that is running.

3. [CTRL]+[SCROLL LOCK]: Break.

When break is detected, interrupt 27 is invoked and the keyboard buffer 
is cleared. Key token 0000h is then inserted into the buffer.

4. [SHIFT]+[PRTSC]: Print Screen.

When print screen is detected interrupt 5 is invoked, the ROS print 
screen function.

5. [INS]: Insert Toggle.

Each time the INS key code (52) is received, except in NUM LOCK mode, 
the INS key toggle bit (bit 7 of RAM location 00417) is inverted.

6. [SCROLL LOCK]: Scroll Toggle.

Each time the SCROLL LOCK key is pressed the scroll key toggle bit (bit 
4 of RAM location 00417) is inverted. Note that CTRL-SCROLL LOCK (break) 
does not flip the scroll toggle.

7 [CAPS LOCK]: Caps Lock Toggle.

Each time the CAPS LOCK key is pressed the Caps Lock toggle bit (bit 6 
of RAM location 00417) is inserted.

8. [NUM LOCK]: Num Lock toggle.

Each time the NUM LOCK key is pressed the Num Lock key toggle bit (bit 5 
of RAM location 00417) is inverted.

9. [ALT]+[NUMERIC KEY PAD 0 to 9]: Absolute Key Token.

When the ALT key is held down, an absolute key token may be entered via 
the numeric keypad. Pressing any other key resets the absolute key token 
to zero ( and inserts the associated ALT-key token for the key pressed). 
When ALT is released the absolute key token modulo 256 is placed into 
the keyboard buffer, unless the token is zero, in which case it is 
discarded.

10. [ENTER] and FIRE Buttons.

When the ENTER key code (74) or one of the two Joystick FIRE button key 
codes (78 or 79) is received an associated key token is obtained from 
the NVR and inserted into the key token buffer.

11. MOUSE Buttons.

The keyboard firmware generates four key codes to indicate when the two 
mouse buttons are pressed and released. When the ROS receives one of 
these codes from the keyboard it does a far call to the address held in 
the Mouse Button interrupt vector (Interrupt 6). A default ROS routine 
is loaded into this vector upon power-up or system reset. This routine 
requests the ROS to insert a key token held in the NVR into the keyboard 
buffer, the token used depends on which mouse button (M1 or M2) is 
received. The mouse button release codes are ignored.

12. [DEL->]: Forward Delete.

When the forward delete key code (code 70) is received a key token is 
obtained from the NVR and placed in the key token buffer.

13. [ALT], [CTRL], [SHIFT], [CAPS LOCK] & [NUM LOCK].

The translation of various key codes into their respective key tokens is 
affected by the current states of these keys (which is stored in 
location 00417). The SHIFT key, while pressed, reverses the current 
state of the CAPS LOCK and NUM LOCK. If more than one of ALT, CTRL, 
SHIFT, NUM LOCK, or CAPS LOCK is active at one time then the order of 
precedence for key code translation is ALT, then CTRL, then SHIFT, then 
CAPS LOCK or NUM LOCK.

CAPS LOCK, when active, converts the key tokens for the lower case 
alphabetic keys (a-z) to their upper case counterparts.

Note that some operating systems (such as DOS Plus) insert their own 
entry points into the interrupt vectors and these interrupt routines may 
exhibit different characteristics than those of the ROS routines 
described here.

2.3.6 INTERRUPT 14: Floppy Disk Controller.

The ROS service routine for interrupt 14 sets bit 7 of the RAM DRIVE 
RESTORE FLAG, to indicate that the Floppy Disk Controller interrupt has 
occurred.

CPU registers are used as follows:

Entry:  No conditions.
Exit:   All flags and registers preserved.

2.3.7 INTERRUPT 16: VDU I/O.

the ROS interrupt 16 service routine provides a set of routines for 
reading and writing characters in alpha and graphics mode. In graphics 
mode the characters are constructed using a character matrix table (See 
section 2.3.20). It also provides facilities for scrolling the screen up 
or down, reading and writing pixels (graphics only) and reading the 
light pen.

CPU registers are used as follows:

Entry: AH = Sub-function number:

            0 - Set VDU Mode.
            1 - Set Cursor Size.
            2 - Set Cursor Address.
            3 - Get Cursor Address.
            4 - Get Light Pen Address.
            5 - Set Display Page.
            6 - Scroll Screen Up.
            7 - Scroll Screen Down.
            8 - Read Character and Attributes.
            9 - Write Character and Attributes.
            10 - Write Character only.
            11 - Write Colour Select Register.
            12 - Write Pixel.
            13 - Read Pixel.
            14 - Write Character in Teletype Emulation Mode.
            15 - Get VDU Parameters.

All other registers as set by the sub-function.

Exit: If selector is greater than 15 then carry is set, else carry is clear.

All other flags and registers as specified by the sub-function.

Alpha modes 0 and 1 require 2000 bytes of VDU RAM while alpha modes 2 
and 3 require 4000 bytes of the VDU RAM. The ROS takes advantage of all 
the (16K bytes) VDU RAM available in alpha modes by supporting multiple 
display pages. This means that application programs can set up a number 
of display pages and switch them as required.

In general parameters passed to ROS routines are not checked and care 
should be taken when choosing unusual parameters as unexpected results 
may occur. In particular be careful of boundary conditions such as 
setting the top of the display window equal to the bottom of the display 
window (for sub-functions 6 and 7) effectively creating a one line 
display. In this instance the scroll screen routines may not perform as 
expected.

VDU Sub-Function 0: Set VDU Mode.

CPU registers are used as follows:

Entry:  AH = 0
        AL = VDU Mode:

    0 - Alpha 25 Rows by 40 Columns.
    1 - Same as Mode 0.
    2 - Alpha 25 Rows by 80 Columns.
    3 - Same as Mode 2.
    4 - Graphics 200 pixels by 320 pixels using palette 1.
    5 - Graphics 200 pixels by 320 pixels using palette 2.
    6 - Graphics 200 pixels by 640.
    7 - Alpha 25 Rows by 80 Columns using Monochrome Adapter.

Exit:   All flags and registers preserved.

In mode 4 palette may be selected by writing the colour select register 
using VDU sub-function 11. The definition of the palettes is contained 
in Section 1.11.2.1, Graphics Mode 1.

When mode 5 is selected it must be followed by a selection of palette 
zero (VDU Colour select register - See 1.11.3) in order to enable 
palette 2.

If the Status-1 default display mode bits (See 1.8.2 DDM1-DDM0) are both 
set, indicating an external monochrome adapter then mode 7 is selected 
regardless of the mode specified in AL.

To select the VDU mode the ROS does the following:

   1. Disable video output.
   2. Reset the Cursor Addresses for all pages to row 0 column 0.
   3. Output the mode to the VDU mode select register.
   4. Reload the VDU controller 6845 emulation registers from the VDU 
      parameter table (which is supplied by interrupt 31).
   5. Clear the (16K bytes of) VDU RAM or the 4K bytes of the monochrome 
      adapter if mode 7 is selected. If an alpha mode is selected, the 
      VDU RAM is filled with white space, i.e. ASCII space (020h) and 
      the default attribute byte held in the NVR. The graphics mode fill 
      is zeros.
   6. Set up the VDU colour select register:
       Set the border colour to the default background colour.
       In graphics modes except mode 6 set intensified foreground colours.
       In mode 6 (Graphics 640 Mode) set white foreground colour.

NOTE: The mode 6 setting of white foreground colour is done by setting 
the VDU Colour Select Register (I/O Address 3D9) to 7. This means that 
in order to subsequently make use of the full 16 colour display 
capability the VDU Colour Select Register must be set to 0F.

   7. For modes 0 to 3 select page zero.
   8. Set the cursor size to start cursor display on scan 6 and end on scan 7.
   9. Enable VDU output.

VDU Sub-Function 1: Set Cursor Size.

This function is only relevant in alpha modes as the hardware cursor is 
not supported in graphics modes. It sets the start and end scan numbers 
of the cursor.

CPU registers are used as follows:

Entry:  AH = 1
        CH = Starting scan of cursor in range 0 to 31d.
        CL = Ending scan of cursor in range 0 to 31d.

Exit:   All flags and registers preserved.

To hide the cursor specify a starting scan value of 31. Also values 
greater than 31 will be interpreted as 'hide cursor' by the ROS.

VDU Sub-Function 2: Set Cursor Address.

This function sets the current row and column addresses of the cursor in 
the specified page.

CPU registers are used as follows:

Entry:  AH = 2
        BH = Page number for modes 0 to 3.
        DH = Cursor Row Address.
        DL = Cursor Column Address.

Exit:   All flags and registers preserved.

In mode 0 and 1 (25 * 40 alpha mode) eight pages (0-7) are supported.
In mode 2 and 3 (25 * 80 alpha mode) four pages (0-3) are supported.

VDU Sub-Function 3: Get Cursor Address.

CPU registers are used as follows:

Entry:  AH = 3
        BH = Page number for modes 0 to 3.
        DH = Cursor Row Address.
        DL = Cursor Column Address.
        
Exit:   DH = Cursor Row Address.
        DL = Cursor Column Address.
        CH = Starting scan of cursor.
        CL = Ending scan of cursor.

All flags and other registers preserved.

In mode 0 and 1 (25 * 40 alpha mode) eight pages (0-7) are supported.
In mode 2 and 3 (25 * 80 alpha mode) four pages (0-3) are supported.

VDU Sub-Function 4: Get Light Pen Address.

This function returns the address of the light pen.

CPU registers are used as follows:

Entry:  AH = 4

Exit:  If Light Pen switch set then
        AH = 1
        DH = Character Row address (0 to 24).
        DL = Character Column address (0 to 79).
        CH = Pixel Row address (0 to 199).
        BX = Pixel Column address (0 to 639).
       If Light Pen switch clear then
        AH = 0
        BX, CH and DX preserved.
       Always
        All flags and other registers preserved.

VDU Sub-Function 5: Set Display Page.

This function sets the active display page.

CPU registers are used as follows:

Entry:  AH = 5
        AL = Page Number to be displayed.

Exit:  All flags and registers preserved.

In mode 0 and 1 (25 * 40 alpha mode) eight pages (0-7) are supported.
In mode 2 and 3 (25 * 80 alpha mode) four pages (0-3) are supported.

VDU Sub-Function 6: Scroll Screen UP.

This function scrolls the active display page, or part of the active 
display page up a specified number of lines.

CPU registers are used as follows:

Entry:  AH = 6
        DH = Bottom Row of area to scroll.
        DL = Right most Column of area to scroll.
        CH = Top row of area to scroll.
        CL = Left most Column of area to scroll.
        BH = Attributes for blank lines scrolled onto the bottom of the 
             scroll area.
        AL = Number of lines to roll up.
             If AL = 0 then blank the specified area.
             If AL not zero then roll specified area up by the number of 
             lines in AL.
             If DH = CH then AL must be zero.

Exit:  All registers preserved.
           Carry is clear and all other flags corrupt.

Scrolling always takes effect on the current active display page.

Hardware scrolling is not supported. Scrolling is achieved by copying 
areas of VDU RAM.

In graphics modes blank lines are filled with attribute byte specified 
in BH to display the current background colour.

Note this function will fail to operate properly if on entry CH = DH and 
AL is not zero. This is also true for all other compatible ROM 
environments.

VDU Sub-Function 7: Scroll Screen DOWN.

This function scrolls the active display page, or part of the active 
display page down a specified number of lines.

CPU registers are used as follows:

Entry:  AH = 7
        DH = Bottom Row of area to scroll.
        DL = Right most Column of area to scroll.
        CH = Top row of area to scroll.
        CL = Left most Column of area to scroll.
        BH = Attributes for blank lines scrolled onto the top of the 
             scroll area.
        AL = Number of lines to roll down.
             If AL = 0 then blank the specified area.
             If AL not zero then roll specified area down by the number of 
             lines in AL.
             If DH = CH then AL must be zero.

Exit:  All flags and registers preserved.

Scrolling always takes effect on the current active display page.

Hardware scrolling is not supported. Scrolling is achieved by copying 
areas of VDU RAM.

Note this function will fail to operate properly if on entry CH = DH and 
AL is not zero. 

VDU Sub-Function 8: Read Character and Attributes.

This function reads the character and its associated attribute byte at 
the current cursor address in a specified display page.

In graphics modes, the character pixel data is generated either from an 
internal character matrix table for characters 0 to 127 or from an 
external character matrix table for characters 128 to 255, the address 
of which is held in interrupt vector 31. See 2.3.22 for additional 
details.

CPU registers are used as follows:

Entry:  AH = 8
        BH = Page to read for alpha modes 0 to 3.
              (Must be zero for all other modes.)

Exit:   AL = Character. (0 if no match found in Graphics Modes).
        AH = Attribute byte. (Unchanged in Graphics modes).
      
All flags and registers preserved.

Refer to 1.11.1 for the definition of the character attribute byte.

VDU Sub-Function 9: Write Character and Attributes.

This function writes a character (or a block of the same character) and 
its associated attribute byte to the current cursor position in a 
specified display page. 

In graphics modes, the character pixel data is generated either from an 
internal character matrix table for characters 0 to 127 or from an 
external character matrix table for characters 128 to 255, the address 
of which is held in interrupt vector 31. See 2.3.22 for additional 
details.

CPU registers are used as follows:

Entry:  AH = 9
        AL = Character to write
        BH = Page to write for alpha modes 0 to 3.
              (Must be zero for all other modes.)
        BL = In alpha modes
                Attributes of character.
             In graphic modes
                Write mode as follows:
                      Bit 7 = 0 for character overwrite mode
                      Bit 7 = 1 for character XOR mode.
                      Bits 0 and 1 = required character colour
                                     (for modes 4 & 5 only).
        CX = Repeat Count.

Exit:   All flags and registers preserved.

The repeat count specifies the number of consecutive locations to which 
the character and attributes are written. In graphics modes all 
characters must fit on the current line.

In graphics mode if bit 7 of BL is set then the data for the specified 
character is exclusively ORed with the data already in the VDU RAM at 
the cursor address.

VDU Sub-Function 10: Write Character Only.

This function writes a character (or a block of the same character) to 
the current cursor position in a specified display page. In alpha modes 
the attribute bytes for all characters written remains unchanged.

In graphics modes, the character pixel data is generated either from an 
internal character matrix table for characters 0 to 127 or from an 
external character matrix table for characters 128 to 255, the address 
of which is held in interrupt vector 31. See 2.3.22 for additional 
details.

CPU registers are used as follows:

Entry:  AH = 10
        AL = Character to write
        BH = Page to write for alpha modes 0 to 3.
              (Must be zero for all other modes.)
        BL = In alpha modes
                BL is not used
             In graphic modes
                Write mode as follows:
                      Bit 7 = 0 for character overwrite mode
                      Bit 7 = 1 for character XOR mode.
                      Bits 0 and 1 = required character colour
                                     (for modes 4 & 5 only).
        CX = Repeat Count.
        
Exit:   All flags and registers preserved.

The repeat count specifies the number of consecutive locations to which 
the character is written.

In graphics mode if bit 7 of BL is set then the data for the specified 
character is exclusively ORed with the data already in the VDU RAM at 
the cursor address.

VDU Sub-Function 11: Write Colour Select Register.

This function writes the VDU Colour Select Register IRGB bits or the 
Palette select bits.

CPU registers are used as follows:

Entry:  AH = 11
        BH = Function select:
             Zero - Set the IRGB bits (3-0) as specified by BL.
             Non Zero - Set the Palette (0 or 1) as specified by BL.

Exit:   All flags and registers preserved.

Changing the palette number (BH non-zero) only has effect in modes 4 and 
5 (320 pixel graphics mode). Refer to section 1.11.3 for further 
details.

VDU Sub-Function 12: Write a Pixel.

This function writes an individual pixel (only valid in graphics modes).

CPU registers are used as follows:

Entry:  AH = 12
        DX = Pixel Row (0 to 199).
        CX = Pixel Column (0 to 639).
        AL = Write Mode:
              Bit 7 = 0 for character overwrite mode.
              Bit 7 = 1 for character XOR mode.
              Bits 0 & 1 = Character Colour for 320 graphics modes.

Exit:   All flags and registers preserved.

The pixel colour specified in AL should be in the range 0 to 3 in modes 
4 and 5 (graphics 320 pixel mode) and in the range 0 to 1 for mode 6 
(graphics 640 pixel mode).

VDU Sub-Function 13: Read a Pixel.

This function is used for reading an individual pixel (only in graphics modes). 

CPU registers are used as follows:

Entry:  AH = 13
        DX = Pixel Row (0 to 199).
        CX = Pixel Column (0 to 639).

Exit:   AL = Colour of the specified pixel.

All flags and other registers preserved.

The pixel colour specified in AL should be in the range 0 to 3 in modes 
4 and 5 (graphics 320 pixel mode) and in the range 0 to 1 for mode 6 
(graphics 640 pixel mode).

VDU Sub-Function 14: Write in TTY Emulation Mode.

This function writes the specified character in Teletype emulation mode 
at the current cursor address in the active display page.

CPU registers are used as follows:

Entry:  AH = 14
        AL = Character to Write.
        BL = In alpha modes
                BL is not used
             In graphic modes
                Write mode as follows:
                      Bit 7 = 0 for character overwrite mode
                      Bit 7 = 1 for character XOR mode.
                      Bits 0 and 1 = required character colour
                                     (for modes 4 & 5 only).
        CX = Repeat Count.

Exit: All flags and registers preserved.

Upon completion of the write the cursor column is incremented by one. If 
the column address is greater than the line length then the column 
address is set to zero and the cursor row address is incremented by one. 

If the incremented row address is greater than the last visible line 
then it is decremented to its original value and the entire page is 
scrolled up one line. In alpha modes the line added to the bottom of the 
page is cleared to spaces with the attributes the same as the first 
character in the previous line. In graphics modes the bottom line is 
cleared to zeros.

The following characters are executed rather than displayed symbolically:

BEL (07h)  Sounds a short (bleep) tone on the speaker.

BS (08h)   Decrements the cursor column one character position unless 
           the column is already zero in which case it is ignored.

CR (0Dh)   Sets the cursor column address to zero.

LF (0Ah)   Increments the cursor row address by one and follows the 
           scroll up procedure as detailed in the paragraph above.

All other control characters are displayed.

VDU Sub-Function 15: Get Current VDU Parameters.

This function returns the current VDU mode, the current display page and 
number of visible columns.

CPU registers are used as follows:

Entry:  AH = 15

Exit:   BH = Current active display page (or zero if in graphics modes 
             or alpha mode 7).
        AH = Number of visible columns (40 or 80).
        AL = Current VDU mode (0 to 7).

        All flags and other registers preserved.

2.3.8 INTERRUPT 17: System Configuration.

This software interrupt returns the current system configuration status 
as defined in RAM locations 00410 and 00411 hex (See section 2.4).

CPU registers are used as follows:

Entry: No conditions.

Exit:  AX = System Configuration status:

  Bit(s)       Function

 14 & 15       Number of printers (1-3).
    13         Not Used.
    12         Set if an optional games adapter is fitted.
    11         Always zero.
  9 & 10       Number of serial interfaces (1-2).
    8          Not Used.
    7          Always zero.
    6          Set if second floppy disk drive is fitted.
  4 & 5        Default VDU mode.
  2 & 3        Always set.
    1          Set if 8087 NDP is installed.
    0          Always set.
          

All flags and other registers preserved.

Section 1.8.2 (Port A - Status-1 Input) contains the default mode states 
as defined in the DDM1 and DDM0 bits.

2.3.9 INTERRUPT 18: Memory Size.

This software interrupt returns the system RAM size as held in system 
locations 00413 and 00414 hex.

CPU registers are used as follows:

Entry: No conditions.

Exit:  AX = Number of 1K memory blocks fitted.
       All flags and other registers preserved.

2.3.10 INTERRUPT 19: Disk I/O.

This software interrupt provides disk read, write, verify, and format 
functions for the drives fitted to the standard floppy disk controller.

CPU registers are used as follows:

Entry:  AH = Disk I/O sub-function selector:

             0 - Initialise the disk sub-system.
             1 - Return the status of the last operation.
             2 - Read a number of consecutive sectors.
             3 - Write a number of consecutive sectors.
             4 - Verify a number of consecutive sectors.
             5 - Format a track.

Exit:   AH = Status Byte:

             0 - Operation completed successfully.
             1 - Incorrect sub-function (or drive) specifier.
             2 - Missing address mark error.
             3 - Disk write protected (write or Format commands only).
             4 - Record not found.
             8 - DMA overrun error.
             9 - Attempted DMA over a 64K segment boundary.
             16 - CRC error.
             32 - Floppy disk controller error.
             64 - Seek error.
             128 - Floppy disk controller timeout (Drive Not Ready).

All other registers as specified by the selected sub-function.

For all disk sub-functions the Carry-Flag (CF) will be clear if no error 
else it is set if an error (and AH = error number). All other flags are 
corrupt.

Disk Sub-Function 0: Initialise Disk Sub-System.

This sub-function performs a total initialisation of the disk interface 
as follows:

1. Reset the FDC (Floppy Disk Controller).
2. Re-configure the FDC parameters to those specified in the disk 
   parameter table (See interrupt 30).

CPU registers are user as follows:

Entry:  AH = 0

Exit:   AH/Flags = Status as specified above
        All registers preserved.

When an error is returned by any other disk I/O sub-function, the 
Initialise Disk sub-function should be called prior ro the next disk 
I/O operation.

Disk Sub-Function 1: Return last Status.

This sub-function returns the status byte and Carry Bit of the last disk 
I/O operation.

CPU registers are used as follows:

Entry:  AH = 1

Exit:   AH/Flags = Status of last disk I/O as specified above. (also AL = AH).
        All other registers preserved.
        Interrupts enabled.

Disk Sub-Function 2: Read Sector.

This sub function reads a number of consecutive sectors. All sectors to 
be read must be on the same track.

CPU registers are used as follows:

Entry:  AH = 2 
        DH = Head Number (0 or 1).
        DL = Drive Number (0 or 1).
        CH = Track Number.
        CL = Starting Sector Number.
        BX = Offset Address of Read Data Buffer.
        ES = Segment Address of Read Data Buffer.
        AL = Number of Sectors to Read.

Exit:   AH/Flags = Status as specified above.
        AL = Number of Sectors successfully read.
             (Corrupt if Timeout error.)
        All other registers preserved.
        Interrupts enabled.

Disk Sub-Function 3: Write Sector.

This sub function writes a number of consecutive sectors. All sectors to 
be read must be on the same track.

CPU registers are used as follows:

Entry:  AH = 3
        DH = Head Number (0 or 1).
        DL = Drive Number (0 or 1).
        CH = Track Number.
        CL = Starting Sector Number.
        BX = Offset Address of Write Data Buffer.
        ES = Segment Address of Write Data Buffer.
        AL = Number of Sectors to Write.

Exit:   AH/Flags = Status as specified above.
        AL = Number of Sectors successfully written.
             (Corrupt if Timeout error.)
        All other registers preserved.
        Interrupts enabled.

Disk Sub-Function 4: Verify Sector.

This sub function verifies a number of consecutive sectors. All sectors to 
be read must be on the same track.

CPU registers are used as follows:

Entry:  AH = 4
        DH = Head Number (0 or 1).
        DL = Drive Number (0 or 1).
        CH = Track Number.
        CL = Starting Sector Number.
        AL = Number of Sectors to Verify.

Exit:   AH/Flags = Status as specified above.
        AL = Number of Sectors successfully verified.
             (Corrupt if Timeout error.)
        All other registers preserved.
        Interrupts enabled.

Since the verification process is halted upon the first occurrence of an 
error, AL represents the number of sectors successfully verified prior 
to the occurrence of an error or total sectors verified if no error.

Disk Sub-Function 5: Format Track.

This sub function formats an entire track.

CPU registers are used as follows:

Entry:  AH = 5
        DH = Head Number (0 or 1).
        DL = Drive Number (0 or 1).
        CH = Track Number.
        BX = Offset Address of Format Buffer.
        ES = Segment Address of Format Buffer.

Exit:   AH/Flags = Status as specified above.
        All other registers preserved.
        Interrupts enabled.

The format buffer contains four bytes of information for each sector on 
the track.

    1. Track Number.
    2. Side Number.
    3. Sector Number.
    4. Sector Size Code.

         0 - 128 Bytes/Sector
         1 - 256 Bytes/Sector
         2 - 512 Bytes/Sector
         3 - 1024 Bytes/Sector

The gap length, filler byte and sectors per track required by the FDC 
Format command are obtained from the DPT (See Disk Parameter Table - 
Section 2.3.21).

2.3.11 Interrupt 20: Serial I/O.

This software interrupt provides functions for character I/O to one of 
the two serial channels and functions for configuring the serial parameters.

Two channels are supported, Logical serial device 0 (COM1:) which is 
always configured and logical serial device 1 (COM2:) which is optional. 
Power-up initialisation determines whether serial device 1 is installed.

CPU registers are used as follows:

Entry:  AH = Sub-Function Selector:

              0 - Initialise Serial Port.
              1 - Write Character to Serial Port.
              2 - Read Character from Serial Port.
              3 - Return Status of Serial Port.

        DH = Logical Channel Number (0 or 1)
        
        All other registers as required by the specified sub-function.

Exit:   AX = Returned Status/Character as defined by the sub-function.
        All flags and other registers preserved.

If logical channel number is out of range (greater than 1) or is not 
fitted then the function is abandoned and the timeout error status (bit 
7 of AH) is returned and all other bits in AX are undefined.

The Logical Serial Device Timeout Count RAM variables (locations 0047C & 
0047D) specify the time out delay (in half seconds) used for channel 
time out. See section 2.4. 

Serial Sub-Function 0: Initialise Port.

This sub-function performs a complete reinitialisation of a serial 
channel. Setting the Baud Rate, Data Bits, Stop Bits and Parity.

CPU registers are used as follows:

Entry:  AH = 0
        DX = Logical Channel Number (0 or 1)
        AL = Hardware Configuration:

  Bit(s)       Function

   5-7         Baud rate Code (0-7).
    4          Set for Even Parity/Clear for Odd Parity.
    3          Set for Parity Enable
    2          Set for 2 Stop Bits/Clear for 1 Stop Bit.
    1          Always set.
    0          Set for 8 Data Bits/Clear for 7 Data Bits.

Exit:   AH = 8250 Line Status register (See section 3.4).
        AL = 8250 Modem Status register.

All flags and other registers preserved.
 
The Baud Rate Code (bits 5 thru 7) is one of the following:

     0 - 110 Baud.
     1 - 150 Baud.
     2 - 300 Baud.
     2 - 300 Baud.
     3 - 600 Baud.
     4 - 1200 Baud.
     5 - 2400 Baud.
     6 - 4800 Baud.
     7 - 9600 Baud.

If the hardware flow control bit in the NVR default VDU mode byte is set 
then RTS is raised true and DTR is set false. Otherwise the current 
state of the control lines is preserved.

Serial Sub-Function 1: Send Character.

This sub-function performs a character out sequence to the selected 
port. The character is output when CTS and the 8250 Tx Holding Register 
Empty status is also true. If the character cannot be sent within the 
time specified in the logical serial device timeout count RAM variable 
then the command is abandoned and AH is returned with bit 7 set.

CPU registers are used as follows:

Entry:  AH = 1
        AL = Character to be sent.
        DX = Logical Channel Number (0 or 1)

Exit:   AH = 8250 Line Status register bits 0 to 6. Bit 7 is set if the 
        channel timed out else bit 7 is clear and the character was sent.

All flags and other registers preserved.

When this sub-function is called, RTS is raised true and if the hardware 
flow bit is disabled then DTR is set as well.

Upon exit both the RTS and the DTR control lines are left in their 
current state.

The Logical Serial Device Timeout Count RAM variables (locations 0047C & 
0047D) specify the time out delay (in half seconds) used for channel 
time out. 

Serial Sub-Function 2: Read Character.

This function attempts to read a character from the specified serial 
port. The character is not read until both Data Ready (DR) and Data Set 
Ready (DSR) status bits are both true. If a character is not received 
within the time specified by the logical device timeout count then the 
command is abandoned and timeout status is flagged.

CPU registers are used as follows:

Entry:  AH = 2
        DX = Logical Channel Number (0 or 1)

Exit:   If character received from 8250 then
           AL = Character received.
           AH = Character status:

  Bit(s)       Meaning 

   7-5         Always '0'.
    4          Break status.
    3          Set if framing error.
    2          Set if parity error.
    1          Set if overrun error.
    0          Always '0'.

If logical channel timed out then
    AH = 080h (bit 7 = 1)

Always
   All flags and other registers preserved.

If the character is received with no errors then AH = 0 on exit.

Upon entry, if no character is available at the serial port DTR is set 
in the Modem Control Register. When a character is read or timeout 
occurs DTR is set false only if hardware flow control is enabled.

If logical channel number is out of range or is not fitted then the 
function is abandoned and the timeout error status (bit 7 of AH) is 
returned and all other bits in AX are undefined. 
The Logical Serial Device Timeout Count RAM variables (locations 0047C & 
0047D) specify the timeout delay (in half seconds) used for channel 
timeout. 
 
Serial Sub-Function 3: Get Channel Status.

This function returns the status os the specified logical channel.

CPU registers are used as follows:

Entry:  AH = 3
        DX = Logical Channel Number (0 or 1)

Exit:   AH = 8250 Line Status register (See section 3.4).
        AL = 8250 Modem Status register.

All flags and other registers preserved.

If logical channel number is out of range or is not fitted then the 
function is abandoned and the timeout error status (bit 7 of AH) is 
returned and all other bits in AX are undefined. 
 
2.3.12 Interrupt 21: Enhanced Function Interrupt.

This software interrupt provides access to the enhanced hardware 
features of the AMSTRAD PC1512.

CPU registers are used as follows:

Entry:  AH = Enhanced function Selector:

         0 - Read and Reset Mouse X and Y Counts.
         1 - Write NVR Location.
         2 - Read NVR Location.
         3 - Write the VDU Colour Plane Write register.
         4 - Write the VDU Colour Plane Read register.
         5 - Write the VDU Graphics Border registers.
         6 - Return ROS Version Number.

All other registers as required by specified sub-function.

Exit:   If sub-function number out of range then
              Carry True.
              All other flags corrupt.
              All registers preserved.
        If sub-function within range then
              All flags and registers as specified by the sub-function.

Enhanced Sub-Function 0: Read/Reset Mouse X/Y Counts.

Read and reset the mouse X and Y count registers. Each register is read 
twice. If the data from two consecutive reads differs then the process 
is repeated until two consecutive reads produce the same data. Upon 
completion of the read procedure the registers are cleared to zero.

CPU registers are used as follows:

Entry:   AH = 0

Exit:    CX = Signed X count.
         DX = Signed Y count.
         Carry False.
         All other flags corrupt.
         All other registers preserved.

Enhanced Sub-Function 1: Write NVR Location.

This sub-function writes a specified location in the Real Time Clock 
Non-Volatile RAM (NVR), re-computes and stores the new checksum value. 
The location written is then read back and compared with the new value 
and if different an error code is returned.

CPU registers are used as follows:

Entry:   AH = 1
         AL = NVR Address to be written (0 to 63).
         BL = NVR Data to be written.

Exit:    AH = Return Code:
            0 - NVR written successfully.
            1 - NVR Address out of range.
            2 - NVR Data write error.
         Carry False.
         All other flags corrupt.
         All other registers preserved.

Although locations 0-13 may be accessed using this function, they are 
used by the RTC hardware and should not be modified with this function.

Section 2.5 (Non Volatile RAM) contains the NVR information layout.

Enhanced Sub-Function : Read NVR Location.

This sub-function reads a specified location in the Real Time Clock Non-
Volatile RAM (NVR). The checksum is computed and compared with the 
actual value and if the NVR checksum is incorrect an error code is returned.

CPU registers are used as follows:

Entry:   AH = 2
         AL = NVR Address to be read (0 to 63).

Exit:    AH = Return Code:
            0 - NVR written successfully.
            1 - NVR Address out of range.
            2 - NVR Data write error.
         AL = Byte read from NVR.
         Carry False.
         All other flags corrupt.
         All other registers preserved.

Section 2.5 (Non Volatile RAM) contains the NVR information layout.

Enhanced Sub-Function 3: Write VDU Colour Plane Write Register.

This sub-function writes an 8-bit value to the VDU Colour Plane Write 
register. Section 1.11.3 contains the details of this register.

CPU registers are used as follows:

Entry:   AH = 3
         AL = Value (I, R, G, B bits)

Exit:    Carry False.
         All other flags corrupt.
         All other registers preserved.

Section 2.5 (Non Volatile RAM) contains the NVR information layout.

Enhanced Sub-Function 4: Write VDU Colour Plane Read Register.

This sub-function writes an 8-bit value to the VDU Colour Plane Read
register. Section 1.11.3 contains the details of this register.

CPU registers are used as follows:

Entry:   AH = 4
         AL = Value (RDSEL1 & RDSEL0)

Exit:    Carry False.
         All other flags corrupt.
         All other registers preserved.

Enhanced Sub-Function 5: Write VDU Graphics Border Register.

This sub-function writes an 8-bit value to the VDU Graphics Mode 2 Border
register. Section 1.11.3 contains the details of this register.

CPU registers are used as follows:

Entry:   AH = 5
         AL = Value to be written.

Exit:    Carry False.
         All other flags corrupt.
         All other registers preserved.

Enhanced Sub-Function 6: Return ROS Version Number.

This Sub-function returns the two part ROS version number.

CPU registers are used as follows:

Entry:   AH = 6

Exit:    BH = Release Number.
         BL = Issue Number.
        
         Carry False.
         All other flags corrupt.
         All other registers preserved.

The Release Number is incremented only when the interface to the ROS is 
changed. The Issue Number is incremented for each version of a 
particular release. A new release always starts with issue number zero.

Note that this function call can be used to detect whether a program is 
running in an Amstrad PC1512. Prior to entry clear the carry flag and 
set BX to zero. Upon return if carry is set or BX is zero then the 
program is not running on an AMSTRAD PC1512.

2.3.13 Interrupt 22: Keyboard I/O.

This software interrupt provides access to the keyboard buffer and the 
current toggle status.

CPU registers are used as follows:

Entry:   AH = Keyboard I/O sub-function selector.
              0 - Get a key token from the keyboard buffer.
              1 - Return Keyboard Buffer status.
              2 - Return current Key Toggle and Key States.

Exit:    If sub-function selector out of range then
              AH = AH - 2
         If sub-function selector within range then
              All flags and registers as specified by sub-function.

Keyboard I/O Sub-Function 0: Get Key Token.

Return the next token from the key token buffer. If no key token is 
available then wait until a key token is available.

CPU registers are used as follows:

Entry:   AH = 0

Exit:    AX = Key Token.
         All flags and other registers preserved.

Keyboard I/O Sub-Function 1: Return Keyboard Buffer Status.

Test whether the key token is empty. If it is empty then return the next 
key token to be taken out of the buffer without removing it from the buffer.

CPU registers are used as follows:

Entry:   AH = 1

Exit:    If key token buffer is empty then
            Zero flag true.
            AX corrupt.
         If one or more tokens in buffer then
            Zero flag false.
            AX = next key token to be removed from the buffer.
         Always
            Interrupts enabled.
            All other flags corrupt.
            All other registers preserved.
         
Keyboard I/O Sub-Function 2: Return Shift States

Return the current value of the shift states (from 00417h).

CPU registers are used as follows:

Entry:   AH = 2

Exit:    AL = Current shift states:

  Bit(s)       Function (Set is key active)

    7          INS
    6          CAPS LOCK
    5          NUM LOCK
    4          SCROLL LOCK
    3          ALT
    2          CTRL
    1          LEFT SHIFT
    0          RIGHT SHIFT

All flags and other registers preserved.
2.3.14 Interrupt 23: Printer I/O

This software interrupt provides access to the three printer channels.

CPU registers are used as follows:

Entry: AH = Printer I/O sub-function selector:

            0 - Send character to printer port.
            1 - Initialise printer port.
            2 - Return printer port status.
            
       DX = Logical Channel Number (0-2).
       
       Other registers as specified by sub-function.
       
Exit:  AH = Printer Port Status (Bits 1-7):

         Bit(s)      Function (Bit Set True)
              
           7         Printer Idle.
           6         Printer Acknowledge.
           5         Paper Out.
           4         Printer Selected.
           3         I/O Error.
         1 & 2       Always Zero.
           0         Zero if I/O successful or set if Timeout.
                     (See sub-functions).

All flags and other registers preserved.

Three logical channels are supported. Logical printer device 0 is the 
system port and is standard to all machines. The power-up initialisation 
sequence determines if additional external printer ports are present. 
When both additional printer interfaces are present, device 1 is the 
external printer port and device 2 is the printer port on the external 
monochrome VDU controller. If only one additional printer interface is 
present it it always logical device 1.

Locations 0478h-047Ah contain the Logical printer Device timeout counts 
(see section 2.4).

Printer Sub-Function 0: Print Character.

This Sub-function attempts to output a character to the specified 
printer port. If the character cannot be sent within the time specified 
by the logical printer timeout count RAM variable then the command is 
abandoned and AH is returned with bit 0 set.

CPU registers are used as follows:

Entry: AH = 0
       AL = Character to be printed.
       DX = Logical Channel Number (0-2).
       
Exit:  AH = Printer Port Status (as given above) or Timeout (Bit 0) set.
       All flags and other registers preserved.

Printer Sub-Function 1: Initialise Printer Channel.

This Sub-function performs a complete reinitialisation of a specified 
printer channel (if present). The printer INIT signal is held low for 
approximately 4 miliseconds. Printer interrupts and auto linefeed are 
disabled.

CPU registers are used as follows:

Entry: AH = 1
       DX = Logical Channel Number (0-2).
       
Exit:  AH = Printer Port Status or Invalid Channel (Bit 0) set.
       All flags and other registers preserved.

Printer Sub-Function 2: Return Channel Status.

This Sub-function returns the status register of the specified logical
printer channel (if present). 

CPU registers are used as follows:

Entry: AH = 2
       DX = Logical Channel Number (0-2).
       
Exit:  AH = Printer Port Status or Invalid Channel (Bit 0) set.
       All flags and other registers preserved.

2.3.15 Interrupt 24: System Restart.

This software interrupt is intended to provide an orderly system restart 
capability. A message is displayed on the active VDU requesting that 
the user "Insert a SYSTEM disk into Drive A" and "Then press any key." 
When the keypress is received, the Disk Bootstrap process (Interrupt 25) 
is invoked.

CPU registers are used as follows:

Entry: No conditions.
       
Exit:  Disk Bootstrap.

2.3.16 Interrupt 25: Disk Bootstrap.

This software interrupt to provide access to the disk bootstrap process 
which is normally executed after power-up initialisation tests.

The ROS attempts to load the bootstrap sector (from drive A, side 0, 
track 0, sector 1) into memory at 07C00. If the bootstrap sector is 
loaded successfully it is given control (far jump to segment 0000 offset 
7C00). If the bootstrap sector cannot be loaded after 10 retries, the 
ROS will display a message prompting the user to "Inset a SYSTEM disk 
into drive A" and "Then press any key." The ROS then waits for the 
keypress and repeats the bootstrap procedure.

CPU registers are used as follows:

Entry: No conditions.
       
Exit:  To program loaded by Disk Bootstrap.

2.3.17 Interrupt 26: System Clock & Real Time Clock.

This software interrupt routine provides access to both the system 
(software maintained) clock location as well as the Real Time Clock 
(RTC) hardware.

CPU registers are used as follows:

Entry: AH = Clock sub-function specifier:

            0 - Get System Clock.
            1 - Set System Clock.
            2 - Get RTC time.
            3 - Set RTC time.
            4 - Get RTC Date.
            5 - Set RTC Date.
            6 - Set RTC alarm.
            7 - Reset RTC alarm.

       All other registers as required by sub-function.

Exit:  All registers as specified by sub-function.

Clock Sub-Function 0: Get System Clock.

This sub-function returns the current value of the 32 bit system clock 
value.

CPU registers are used as follows:

Entry: AH = 0

Exit:  DX = Least Significant Word of the clock count.
       CX = Most Significant Word of the clock count.
       AL = 24 Hour Flag:
            0 if not past 24 hours.
            1 if past 24 hours.

       All flags and other registers preserved.

The 32 bit system clock is incremented every 54 milliseconds by the 
ticker hardware interrupt routine. When the count reaches the 24 hour 
value (000185000h) the 24 Hour flag is set and the system clock count is 
reset to zero.

Note that the 24 hour flag is reset to zero after it has been read.

Clock Sub-Function 1: Set System Clock.

This sub-function sets the current value of the 32 bit system clock 
value.

CPU registers are used as follows:

Entry: AH = 1
       DX = Least Significant Word of the clock count.
       CX = Most Significant Word of the clock count.
       
Exit:  All flags and registers preserved.

Clock Sub-Function 2: Get RTC Time.

This sub-function gets the current time from the Real Time Clock.

CPU registers are used as follows:

Entry: AH = 2
       
Exit:  If RTC not operating then
          Carry True.
          CX DX preserved.
       If RTC operating then
          Carry False.
          CH = Hour (BCD).
          CL = Minute (BCD).
          DH = Second (BCD).
       Always
          All other flags corrupt
          All other registers preserved.

Clock Sub-Function 3: Set RTC Time.

This sub-function sets the Real Time Clock time.

CPU registers are used as follows:

Entry: AH = 3
          CH = Hour (BCD).
          CL = Minute (BCD).
          DH = Second (BCD).
          DL = 1 to enable daylight savings option (otherwise 0).
       
Exit:  If RTC not operating then
          Carry True.
       If RTC operating then
          Carry False.
       Always
          All other flags corrupt
          All other registers preserved.

When the daylight savings option is set it enables two special updates 
of the current time. On the last Sunday in April, the time increments 
from 1:59:59 AM to 3:00:00 AM. Also on the last Sunday in October the 
time increments from 1:59:59 AM to 1:00:00 AM.

Note that this option also disables the alarm function.

Clock Sub-Function 4: Get RTC Date.

This sub-function gets the current date from the Real Time Clock.

CPU registers are used as follows:

Entry: AH = 4
       
Exit:  If RTC not operating then
          Carry True.
          CX DX preserved.
       If RTC operating then
          Carry False.
          CH = Century (BCD).
          CL = Year (BCD).
          DH = Month (BCD).
          DL = Day of Month (BCD).
       Always
          All other flags corrupt
          All other registers preserved.

The century byte is set to 19 (BCD) if the year is 80 (BCD) or above 
otherwise it is set to 20 (BCD).

Clock Sub-Function 5: Set RTC Date.

This sub-function sets the Real Time Clock date.

CPU registers are used as follows:

Entry: AH = 5
          CH = Century (BCD) [Ignored].
          CL = Year (BCD).
          DH = Month (BCD).
          DL = Day of Month (BCD).
       
Exit:  If RTC not operating then
          Carry True.
       If RTC operating then
          Carry False.
       Always
          All other flags corrupt
          All other registers preserved.

Century is ignored and is computed as described in clock sub-function 4.

Clock Sub-Function 6: Set RTC Alarm.

This sub-function sets the alarm time and arms the Real Time Clock alarm 
interrupt. The alarm interrupt will occur when the current time matches 
the alarm time. An application program which uses this function must 
first write the address of its alarm interrupt routine into interrupt 
vector 10.

CPU registers are used as follows:

Entry: AH = 6
          CH = Hour (BCD).
          CL = Minute (BCD).
          DH = Second (BCD).
       
Exit:  If RTC alarm already set then
          Carry True.
       If RTC alarm not already set then
          Carry False.
       Always
          All other flags corrupt
          All other registers preserved.

Clock Sub-Function 7: Kill RTC Alarm.

This sub-function disarms the Real Time Clock alarm function.

CPU registers are used as follows:

Entry: AH = 7
       
Exit:  All flags and registers preserved.

2.3.18 Interrupt 27: Keyboard Break Interrupt.

This software interrupt is invoked by the keyboard hardware interrupt 
routine when a keyboard break ([CTRL]+[NUM LOCK]) is detected.

The power-up initialisation process loads the address of a dummy break 
handler routine which does an interrupt return (IRET) instruction.

Application programs which supply a keyboard break interrupt must conform 
to the following register conventions:

Entry: DS = 0040h (Spanning the ROS data).

Exit:  All registers must be preserved except AX, BX, CX, DX, DS and 
       Flags which may be corrupt. 

The supplied interrupt routine must not invoke any other ROS interrupts 
from within itself but may modify any of the system RAM locations used 
by the ROS.

2.3.19 Interrupt 23: External Ticker Interrupt.

This software interrupt is called from within the System Clock hardware 
interrupt routine. It is initialised by power-up with a dummy handler 
which returns from interrupt by doing an IRET instruction. It can be 
used by application programs which require a process to be run at a 
regular interval.

Application programs which supply an external ticker interrupt must 
conform to the following register conventions:

Entry: DS = 0040h (Spanning the ROS data).

Exit:  All registers must be preserved except AX, DX, DS and Flags which 
       may be corrupt. 

The supplied interrupt routine must not invoke any other ROS interrupts 
from within itself but may modify any of the system RAM locations used 
by the ROS.

2.3.20 Interrupt 29: VDU Parameter Table.

This interrupt vector location contains the 32-bit address of the VDU 
parameter table used in setting up the video hardware when changing the 
VDU mode. Upon power-up or after a reset, the initialisation process 
loads the ROM table address into the vector location (0074-0077 hex).

The VDU parameter table consists of four consecutive 16 byte entries. 
Each entry contains an initialisation quantity for each of the emulated 
MC6845 CRTC registers (See section 1.11.5). When a new VDU mode is 
selected the table entry is used to initialise the VDU as follows:

    Table Entry         VDU Mode

           0            0 - Alpha 25 by 40 Characters.
           0            1 - Alpha 25 by 40 Characters.
           1            2 - Alpha 25 by 80 Characters.
           1            3 - Alpha 25 by 80 Characters.
           2            4 - Graphics 200 by 320 Pixels, Palettes 0 or 1.
           2            5 - Graphics 200 by 320 Pixels, Palette 2.
           2            6 - Graphics 200 by 640 Pixels.
           3            7 - Alpha 25 by 80 characters using monochrome adapter.
                   

The table contains the following initialisation data:

 Register                               Entry   Entry  Entry  Entry
 Number     Function                      0       1      2      3

   R0      *Horizontal Total             56     113      56    97
   R1       Horizontal Displayed        [40]    [80]    [40]   80
   R2      *Horizontal Sync Position     45      90      45    82
   R3      *Horizontal Sync Width        10      10      10    15
   R4      *Vertical Total               31      31     127    25
   R5      *Vertical Total Adjust        06      06      06    06
   R6       Vertical Displayed          [25]    [25]   [100]   25
   R7      *Vertical Sync Position       28      28     112    25
   R8      *Interlace                    02      02      02    02
   R9       Maximum Raster Address       07      07      01    13
   R10      Cursor Start Raster          06      06      06    11
   R11      Cursor End Raster            07      07      07    12
   R12      Start Address (H)            00      00      00    00
   R13      Start Address (L)            00      00      00    00
   R14      Cursor Location (H)          00      00      00    00
   R15      Cursor Location (L)          00      00      00    00

Registers marked '*' are not software programmable in the emulated 
MC6845 CRTC implementation and their corresponding values are place 
holders in the table.

The two sets of values marked by '[]' have no effect on the display, but 
a zero value in either register will cause the whole screen to display 
the border colour.

2.3.21 Interrupt 30: Disk Parameter Table.

This interrupt vector contains the 32-bit address of the parameter table 
of configuration parameters. Upon power-up or after a reset, the 
initialisation process loads the ROM table address into this vector 
location (0078-007B hex).

The Disk Parameter Table consists of 11 bytes as follows:

     Byte         Function                                           Value

      0           2nd byte of the disk controller specify command.     208
                  (6 Ms Step Rate, Head Unload delay disabled.)    
      1           3rd byte of disk controller specify command.          0
                  (Head Load Delay disabled.)                      
      2           Motor off timeout (approximately 5 seconds).         100
      3           Sector size selector (512 bytes).                     2
      4           End of Track (sector 9).                              9
      5           Gap length for Read/Write commands.                   42
      6           DTL - Data length.                                   255
      7           Gap length for format command.                        80
      8           Filler byte for format command.                      246
      9           Head Settling Delay (15 Ms).                          15
     10           Motor on Delay (500 Ms).                               4

2.3.22 Interrupt 31: VDU Matrix Table.

This interrupt vector location contains the 32-bit address of the VDU 
matrix table used in graphics modes for generating pixel data for 
characters 128 to 255.

Upon power-up or after a reset, the initialisation process loads the 
vector location (007C-007F) with all zeros to indicate that no external 
VDU matrix table is loaded.

Each of the 128 character table entries consists of eight bytes, one for 
each character scan. The first byte is the top scan value and the last 
byte is the bottom scan value. The MSB, bit 7, is the left most pixel 
and the LSB, bit 0, is the right most pixel of the scan. A set bit 
displays the foreground colour and a reset bit displays the background 
colour.

2.4 RAM Variables.

The System RAM address space from 00300 to 00500 is used by the ROS for 
variable storage. The following table lists the variables and their 
usage. They are classified either as Byte (8-bit), Word (16-bit), Long 
Word (32-bit) or Buffer (greater than 32-bit) storage locations.

Location(s)         Usage

00300-003FF         Initialisation Stack (Buffer).
                    Used as stack area only during initialisation.
                
   00400            Logical Serial Device 0 Base I/O Address (Word).
                    Contains the base address of logical serial device 0.
                    Initially the System Asynchronous Serial port address.
                
   00402            Logical Serial Device 1 Base I/O Address (Word).      
                    Contains the base address of logical serial device 1. 
                    Initially the System Asynchronous Serial port or
                    zero if it is not present at initialisation.
                
 0404-0407          Reserved.
                
   00408            Logical Printer Device 0 I/O Address (Word).
                    The base address of logical printer device 0.
                    Initially the System Parallel Printer port.
                
   0040A            Logical Printer Device 1 I/O Address (Word).
                    The base address of logical printer device 1.
                    Initially the external parallel printer port
                    if it is present else it points to the external 
                    monochrome VDU controller if it is present.
                    If neither is present it is initialised to zero.
                     
   0040C            Logical Printer Device 2 Base I/O Address (Word).
                    Initially points to the external monochrome VDU controller
                    if both the external parallel printer port and the
                    external monochrome VDU controller are present.
                    If either is not installed initialised to zero.
                
   0040E            Reserved (Word).
                
   00410            System Configuration Status (Word).
                    Contains the System Configuration as follows:
                
                      Bit(s)        Function
                     
                      14 & 15       Number of printers (1-3).
                        13          Not Used.
                        12          Set if optional games adapter fitted.
                        11          Always zero.
                       9 & 10       Number of serial interfaces (1 or 2).
                         8          Not Used.
                         7          Always zero.
                         6          Set if second floppy disk drive is fitted.
                       4 & 5        Default VDU mode.
                       2 & 3        Always set.
                         1          Set if 8087 NDP is installed.
                         0          Always set.
                
   00412            Reserved (Byte).
                
   00413            Total RAM Size (Word).
                    Initially set to the number of 1K User (System) RAM
                    Blocks installed.
                
   00415            Extra RAM Size (Word).                             
                    Initially set to the number of 1K User (System) RAM
                    Blocks installed minus 64.                         
                
   00417            Key Toggles and Key States (Byte).
                    This byte is used to record the state of the Key
                    Toggles (bits 4-7) and Key States (bits 0-3) as follows:
                
                        Bit        Key (Bit set if active)
                       
                         7         INS
                         6         CAPS LOCK
                         5         NUM LOCK
                         4         SCROLL LOCK
                         3         ALT
                         2         CTRL
                         1         LEFT SHIFT
                         0         RIGHT SHIFT
                                
   00418            Keys down (Byte).
                    This byte is used to record the state of the toggle keys
                    so that they do not repeat when the key is held down.
                
                        Bit        Key (Set if down)
                       
                         7         INS
                         6         CAPS LOCK
                         5         NUM LOCK
                         4         SCROLL LOCK
                
                    Bit 3 is set when Pause state ([CTRL][SCROLL LOCK]) is
                    active. Bits 0-2 are unused and initially zeroed.
                
   00419            Absolute Key Token Number (Byte).
                    When an absolute key token number is entered via ALT and
                    the numeric key pad, this variable holds the current
                    state of the token.
                
   0041A            Key Token Buffer Out Pointer (Word).
                    This variable holds the absolute offset to the next
                    key token to be removed from the key token buffer.
                    Note that the ROS assumes that the buffer has a segment
                    paragraph address of 0040h.
                
   0041C            Key Token Buffer In Pointer (Word).
                    This variable holds the absolute offset to the next empty
                    position in the key token buffer. The buffer is empty when
                    this location is the same as the Out Pointer.
                
                    Key Token Buffer (Buffer).
   0041E            The Key Token Buffer is a 16 word circular buffer used to
                    store up to 16 key tokens.
                
   0043E            Drive Restore Flag (Byte).
                    Each floppy disk drive has a restore flag associated with
                    it (bit 0 for drive 0 and bit 1 for drive 1).
                    If the restore flag for the specified flag is reset prior
                    to any disk access (read/write/verify/format), then the
                    restore command is issued to the FDC for that drive. If
                    successful then the associated flag bit is set. When the
                    initialise sub-function of the disk interrupt is called
                    the restore flag is cleared.
                    Bit 7 is used for handling the FDC hardware interrupts.
                
  0043F             Drive Motor Flag (Byte).
                    When a disk drive motor is running then either bit 0 or 
                    bit 1 will be set to which drive (0 or 1 respectively)
                    is selected.
                
  00440             Drive Motor Timeout Counter (Byte).
                    After disk operation the motor off timeout count is copied
                    from the Disk Parameter Table (See interrupt 30) into this
                    variable. Each time the system clock interrupt is executed
                    the count is decremented. When it reaches zero the Drive 
                    Motor Flag is reset.
                
  00441             Disk Status (Byte).
                    This byte holds the status returned by the last disk 
                    operation. (See section 2.3.19 Disk I/O Interrupt -
                    Sub-Function 1.)
                
  00442             FDC Results Buffer (Buffer).
                    This seven byte buffer is used for storage of the 
                    FDC status information returned upon the completion
                    of a disk I/O operation.
                
  00449             Current VDU Mode (Byte).
                    The current VDU mode in the range of 0-7 is stored here.
                
  0044A             Visible VDU Columns (Word).
                    The number of visible character columns currently being
                    displayed is stored here.
                
  0044C             VDU Buffer Size (Word).
                    This word holds the amount of VDU RAM used by the ROS
                    to display one page as defined below:
                
                      Mode(s)     Size
                     
                       0 & 1      2048
                       2 & 3      4096
                        4-6       16384
                         7        4096
                                
  0044E             VDU Display Start Address (Word).
                    Contains the origin of the currently active VDU 
                    display page.
                
  00450             Cursor Address Buffer (Buffer).
                    This 16 byte buffer contains the row and column
                    address for up to eight display pages.
                
  00460             Cursor End Scan (Byte).
                    This byte contains the current end scan number that 
                    was programmed into the VDU controller.
                
  00461             Cursor Start Scan (Byte).                             
                    This byte contains the current start scan number that 
                    was programmed into the VDU controller.             
                
  00462             VDU Active Display Page (Byte).
                    This byte contains the selected page number.
                
  00465             VDU I/O Address (Word).
                    This word contains the I/O address of the VDU interface
                    currently in use. For all modes except 7 this is the
                    internal emulated MC6845 CRTC device. For mode 7 it is
                    the external Monochrome VDU controller.
                
  00466             Current VDU Colour Select Register (Byte).
                    This byte contains a copy of the data loaded into the 
                    VDU colour select register.
                
 00467-0046B        Reserved
                
  0046C             System Clock (Long Word).
                    The 32 bit system clock count.
                
  00470             24 Hour Flag (Byte).
                    When the system clock reaches 000185000h then it is
                    cleared and this flag byte is set to 0FFh.
                    Note that reading the clock via interrupt 26 clears this
                    flag.
                
  00471             Break (Byte).
                    This byte is initially set to zero. Each time Break
                    ([CTRL]+[NUM LOCK]) is detected, bit 7 is set. 
                    An application program using this bit to detect break
                    must reset bit 7 when it detects the break event.
                
  00472             System Reset Flag (Word).
                    When system reset ([CTRL]+[ALT]+[DEL]) is detected this
                    location is set to 01234h  prior to issuing a system
                    reset. The power-up self test routine then recognizes 
                    this pattern and does not repeat the RAM tests.
                
 00474-00477        Reserved for Hard Disk BIOS ROM.
                
  00478             Logical Printer Device 0 Timeout Count (Byte). 
                
  00479             Logical Printer Device 1 Timeout Count (Byte). 
                
  0047A             Logical Printer Device 2 Timeout Count (Byte). 
                
                    Ŀ
                    Locations 00478-0047A specify how long the ROS should
                    wait in half second multiples, while trying to output
                    a character to a logical printer channel. They are   
                    initially set to 20 (10 second timeout).             
                    
                
  0047B             Reserved.
                
  0047C             Logical Serial Device 0 Timeout Count (Byte). 
                
  0047D             Logical Serial Device 1 Timeout Count (Byte). 
                
                    Ŀ
                    Locations 0047C & 0047D specify the length of the    
                    wait time in half second intervals for character I/O 
                    to a particular logical serial channel. All counts   
                    are set to 1 (for a 1/2 second timeout).             
                    
                
  0047E             Reserved.
                
  00480             Key Token Buffer Start Address (Word).
                    Offset pointer to the start of the key token buffer.
                    Note that the assumed buffer segment paragraph
                    address is 0040h.
                
  00482             Key Token Buffer End Address (Word).
                    Offset pointer to the start of the key token buffer.
                
  00500             Print Screen Status (Byte).
                    This byte holds the current print screen status:
                
                    Value        Meaning
                   
                       0         Print Screen completed OK.
                       1         Print Screen in progress.
                      255        Print Screen abandoned due to timeout.



2.4 Non-Volatile RAM (NVR)

The first 40 bytes of the battery backed up RAM within the RTC hardware are
for system parameter storage as follows:

   Bytes         Usage                                       Default
 
   0-9           Time and Date parameters.                     --
    10           RTC Control Register A.                      070
    11           RTC Control Register B.                      002
    12           RTC Control Register C.                       --
    13           RTC Control Register D.                       --
  14-19          Time and Date when machine last used.         --
    20           User RAM Checksum.                       
  21-22          Enter Key translation token.                 1C0D
  23-24          Forward Delete key translation token.        2207
  25-26          Joystick Fire Button 1 translation token.    FFFF
  27-28          Joystick Fire Button 1 translation token.    FFFF
  29-30          Mouse Button 1 translation token.            FFFF
  31-32          Mouse Button 1 translation token.            FFFF
    33           Mouse X direction scaling factor.            00A
    34           Mouse X direction scaling factor.            00A 
    35           Initial VDU mode and drive count.            020
    36           Initial VDU Character attributes.            007
    37           Size of RAM disk in 2K blocks.               000
    38           Initial system UART hardware setup byte.     0E3
    39           Initial system UART hardware setup byte.     0E3 
  40-63          Unused.                                       --

After power-up or upon system reset the NVR is checksummed as part of 
initialisation. If the lower byte of the sum is not 0AAh or if the 
battery voltage low bit is set in the RTC status register, then the 
values in the default column are loaded into their respective locations 
an a warning message is displayed on the VDU. Those locations without 
defaults (marked with '--') are not changed.

The default key token values in bytes 25 to 32 is a special value (FFFF) 
which signals the keyboard hardware interrupt to ignore the key press 
rather than to insert the key token into the buffer.

The initial VDU mode (byte 35) is used to set up the system status-1 
channel. (DDM - bits 4 & 5. See 1.8.2 for the valid combinations.) Bits 
4 and 5 of byte 35 are set up correspondingly. Bit 6 is set if two 
drives are fitted else it is cleared. The default version of byte 35 has 
bit 6 set (two drives) and bits 4 & 5 set to 1 & 0 (Colour, alpha, 80x25 
chars). 

Bit 7 of byte 35 is used to enable or disable the Serial I/O flow 
control option. Refer to section 2.3.11 for serial I/O and flow control 
details.

The initial VDU character attribute (byte 36) is written to all the 
attribute bytes of the VDU buffer when one of the alpha modes is 
selected. The default value selects a white foreground on a black 
background. 

The RAM disk size (byte 37) is used by the MS-DOS and DOS Plus operating 
systems to specify their RAM disk setup size.

The initial UART parameters (bytes 38 and 39) specifies 9600 baud, 8 
data bits, 1 stop bit and no parity. These values are loaded to their 
respective serial channel by the Serial I/O Initialise sub-function (See 
Section 2.3.11: Interrupt 20).

2.6 ROS Messages

The ROS outputs a number of messages during initialisation and self test 
as detailed below. The language in which these messages are displayed is 
dependent of the three option links connected to the three least 
significant bits of the system printer port status. (See Table 3.1 for 
the interpretation of the three link bits.)

2.6.1 Non-Fatal ROS Messages

The following messages are displayed on the VDU (in the default display 
mode as specified by the NVR) in the situations as described. The 
initialisation process is allowed to complete even though some of them 
may represent self test failures.

Please wait

     This message is displayed on the top line of the screen after Power-Up
     or after a System Reset ([CTRL}+[ALT]+[DEL]) from the keyboard. A dot is 
     displayed after it for each major hardware self test segment completed
     successfully.

AMSTRAD PC nnnK(Vv.i) Last used at hh:mm on dd mm yy

     This message is displayed after the successful completion of all 
     self tests, where:

     nnn          = the RAM size in kilobytes.
     v.i          = the ROS Version (v) and Issue (i) number.
     hh:mm        = the hours (hh) and the minutes (mm) of last on time.
     dd mm yy     = the day (dd), the calendar month (mm) and the year (yy)
                    of the last date used.

Please fit new batteries

     This message is displayed below the AMSTRAD PC message when it is noted
     that the RTC battery voltage low bit (VRT) is set (indicating that there
     is either no battery installed or that the battery is very nearly flat).

Check keyboard and mouse

     This message is displayed when the keyboard self test firmware does 
     not respond with the test pass (0AAh).

Insert a SYSTEM disk into drive A
Then press any key

     This message set is displayed when the floppy disk bootstrap is unable
     to successfully read the bootstrap sector from drive A after 10 retries.

Error: External ROM checksum incorrect: ROM address = nnnnnh

     This message is displayed when the checksum on an external ROM is not
     zero (See section 2.1-16). The physical address of the ROM is displayed
     in five (nnnnn) hexadecimal digits.

2.6.2 Fatal ROS Messages

The following messages indicate that a self test segment has failed and 
that initialisation cannot continue. In this situation the machine must 
be switched off and on again in order to reinitiate operations. The VDU 
is switched to 80 column alpha mode and cleared prior to displaying any 
of these messages.

     Error: Faulty SYSTEM RAM
     Error: Faulty VDU RAM
     Error: Faulty interrupt controller
     Error: Faulty direct memory access controller
     Error: Faulty floppy disk controller or disk drive
     Error: Faulty interval timer
     Error: Faulty system status register
     Error: Faulty real time clock
     Error: Faulty VDU controller
     Error: Faulty system printer port
     Error: Faulty system serial port
     Error: Faulty mouse coordinate register
     Error: Faulty ROS ROM checksum
     Error: Faulty memory (parity error)

As is evident from the message content, the faulty system component is 
named. When one of these failures occurs, no other testing is run since 
further testing may require use of the failing component. For this 
reason the system is placed in a non-interruptable loop. Failures of 
this sort are not expected to occur even intermittently. When any self 
test failure does occur it should be referred to a qualified AMSTRAD 
service facility for further diagnostic testing.



