List of Figures
| Table of Contents | List of Figures | List of Examples | List of Tables |
- Figure 1-1. CPU Access to Memory
- Figure 1-2. CPU Access to Device Registers
- Figure 1-3. Device Access to Memory
- Figure 1-4. Device Access Through a Bus Adapter
- Figure 1-5. The 32-Bit Address Space
- Figure 1-6. MIPS 32-Bit Virtual Address Format
- Figure 1-7. Main Parts of the 64-Bit Address Space
- Figure 1-8. MIPS 64-Bit Virtual Address Format
- Figure 1-9. Address Decoding for Physical Memory Access
- Figure 3-1. Overview of Device Open
- Figure 3-2. Overview of Device Control
- Figure 3-3. Overview of Programmed Kernel I/O
- Figure 3-4. Overview of Memory Mapping
- Figure 3-5. Overview of DMA I/O
- Figure 5-1. Bit Assignments in SCSI Device Minor Numbers
- Figure 13-1. Relationship of VME Bus to System Bus
- Figure 13-2. VMECC, the VMEbus Adapter
- Figure 13-3. I/O Address to System Address Mapping
- Figure 13-4. VMECC Contribution to VME Handshake Cycle Time
- Figure 16-1. Overview of Network Architecture
- Figure 17-1. High-Level Overview of EISA Bus in Indigo2
- Figure 17-2. Encoding of the EISA Manufacturer ID
- Figure 18-1. The SysAD Bus in Relation to GIO